Part II: Introduction to SiFive RISC-V Core IP
Part II: Introduction to SiFive RISC-V Core IP
This webinar focuses on embedded developers who are interested in learning more about the RISC-V architecture. Part two introduces the SiFive RISC-V Core IP Products; the E31 RISC-V Core IP and the E51 RISC-V Core IP.
Webinar Info
One hour
2017-10-17
Hosted by
Drew Barbier
Field Engineer at SiFive, Inc.Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great.
Jack Kang
VP of Product and Business Development @Sifive, Inc.Jack has held a variety of senior business development, management, and product marketing roles at both NVIDIA and Marvell, with a track record of successful, large scale design wins. Jack started his career as a frontend design engineer, focusing on CPU architecture and design. Jack received his BS degree in Electrical Eng. and Computer Science from UC Berkeley.
About Us
SiFive was founded by the creators of the free and open RISC-V architecture as a reaction to the end of conventional transistor scaling and escalating chip design costs.