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Resources

sifive-risc-v-cores-for-ssd-controllers.pdf



Overview of SiFive Cores for the Storage Market



SiFive RISC-V Cores for SSD Controllers 

451_Reprint_SiFive_Enterprise_Apps_12JUL2021.pdf

SiFive Performance, Intelligence processor lines extend RISC-V to applications, AI/ML markets

SiFive Shepherds RISC-V ISA to Enterprise Applications, Broader Adoption

P650 Pumps Up Performance by 50%.pdf

SiFive Performance™ P650 ups performance 50% over P550, introduced just 6 months prior



![Message from CEO](https://images.prismic.io/sifive/7db001ae-95ab-41f8-982e-95cdaafbc78e_message-from-CEO.jpg?auto=compress,format)
*The coronavirus pandemic has disrupted the global community—a stark reminder that we are citizens of one world and must work in unison to stop the spread. Teams of scientists from multiple countries are working with different vaccine technologies to find a solution. We applaud them all for their efforts and eagerly anticipate their quick success.*

At SiFive, we are closely monitoring the situation and following all CDC recommendations, including having all of our teams work from home. We remain fully engaged with our customers, partners and each other, and everything remains business-as-usual. In fact, we continue to establish new partnerships, build and launch world-class product solutions, host virtual events, and expand our team. Please read more below to see these highlights in detail.

We wish all of you good health, patience and solidarity during this challenging time; we have no doubt that the world will emerge stronger than ever.

With regards,<br>
Naveed Sherwani<br>
President & CEO<br>
SiFive, Inc.

Company Highlights<br>
- Former Google, Tesla and Apple Engineering Executive, Chris Lattner, has joined SiFive as Senior Vice President of Platform Engineering. Chris is known for leading the creation of numerous software technologies, including the LLVM compiler infrastructure, Clang C and C++ compilers, MLR machine learning infrastructure, and the Swift programming language that powers Apple’s ecosystem. For more information, you can read the [press release](https://www.sifive.com/press/former-google-and-tesla-engineer-chris-lattner-to-lead) and Chris’s [blog](https://www.sifive.com/blog/with-sifive-we-can-change-the-world) describing how he believes SiFive is uniquely positioned to transform the silicon industry.

- Leading Industry Veteran Shubham “Sam” Maheshwari, has joined SiFive as CFO. Sam is highly experienced in silicon industry finance, operations and acquisitions, and is known for achieving results. [Learn more](https://www.sifive.com/press/leading-industry-veteran-joins-sifive-as-chief-financial).

New Solutions<br>
- Cloud Accelerated Idea-to-Silicon – SiFive’s mission is to accelerate chip design, closing the time between the definition of a chip to silicon being available - we call this the “idea-to-silicon” journey. The solutions to modern computing challenges increasingly require domain-specific accelerators, which are silicon chips designed to solve a specific problem with built-in adaptability to provide flexibility for shifting workloads [Learn more](https://www.sifive.com/blog/cloud-accelerated-idea-to-silicon).

- ![](https://images.prismic.io/sifive/dd2f41b6-0963-49f1-8a16-b7db05c0d7cf_sifive-insight-logo-nl.png?auto=compress,format)
Advanced Trace and Debug Portfolio, SiFive Insight – This comprehensive debug and trace solution offers SoC designers class-leading debug capabilities to bring-up first silicon, support hardware and software integration, and debug software applications. [Learn more](https://www.sifive.com/soc-ip/sifive-insight). Additionally, there is a [blog](https://www.sifive.com/blog/introducing-sifive-insight) that details the trace and debug features and functions of the SiFive Insight portfolio.

Recent Partner News<br>
- SiFive is collaborating with Synopsys using their Fusion Design Platform™ and Verification Continuum™ Platform to enable rapid cloud-based design of next-generation customer silicon products. Together with Synopsys, SiFive is also collaborating with Microsoft Azure to lower barriers to custom SoC design.
[Learn more](https://www.prnewswire.com/news-releases/sifive-selects-synopsys-fusion-design-platform-and-verification-continuum-platform-to-enable-rapid-soc-design-301029184.html).

- SiFive and CEVA partner to bring machine learning processors to mainstream markets. [Learn more](https://bit.ly/3a78BsA).

RISC-V Ecosystem<br>
- SEGGER Microcontroller GmbH announced comprehensive support for the SiFive Insight debug and trace pre-integrated in RISC-V processor cores.
[Learn more](https://www.segger.com/news/segger-announces-comprehensive-support-for-sifive-insight-debugtrace-platform/).

-  RISC-V is not an “open-source processor” – Krste Asanovic, Chairman of the Board of the RISC-V Foundation, wrote a [blog](https://riscv.org/2020/02/risc-v-is-not-an-open-source-processor-krste-asanovic-chairman-of-the-board-risc-v/) addressing the confusion about the difference between a specification and an implementation.

- Chips that pass in the night: How risky is RISC-V to Arm, Intel and the others? Very – A great [article](https://bit.ly/2VpNnBd) on RISC-V innovation was published by *The Register*, a global online tech publication.

- There are more RISC-V updates in the latest Linux 5.6 release. These include DT entry for the GPIO controller in the SiFive Freedom U540 SoC, the world's first Linux-capable multi-core RISC-V processor, and DTS updates for our HiFive Unleashed, the development board incorporating the U540 SoC. [Learn more](https://bit.ly/2Xxqs9J).

- Celebration of IoT Day 2020: How Open Hardware & Software is Stimulating IoT Innovation – SiFive participated in IoT Day (April 9 – Online) with other RISC-V Foundation members to reflect on how the free and open RISC-V ISA enables IoT innovation.
[Learn more](https://bit.ly/2VrUj0E).

Other Highlights<br>
- Well-known industry blogger, Dumi Loghin, wrote about “How to Increase the Size of the Data Memory on SiFive FE310 RISC-V” [Read more](https://bit.ly/3elguOw).

- [Part 1: Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V](https://www.sifive.com/blog/part-1-fast-access-to-accelerators-enabling-optimized-data-transfer-with-risc-v)

- [Part 2: High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V](https://www.sifive.com/blog/part-2-high-bandwidth-core-access-to-accelerators-enabling-optimized-data-transfers-with-risc-v)

- [Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V](https://www.sifive.com/blog/part-3-high-bandwidth-accelerator-access-to-memory-enabling-optimized-data-transfers-with-risc-v)

- [Part 4: High-Performance Interconnect for Accelerators: Enabling Optimized Data Transfers with RISC-V](https://www.sifive.com/blog/part-4-high-performance-interconnect-for-accelerators-enabling-optimized-data-transfers-with-risc-v)

- SiFive Presented at the Mentor Graphics Emulation Forum in Bangalore (February 18) and Hyderabad, India (February 20):
*Verification of Ethernet-PCS IP with Mentor’s Veloce Emulator*, by Shivaram Venkatesh, Sr. Marketing Engineer. [Learn more](https://openfive.com/case-study/).

![SiFive Connect logo](https://images.prismic.io/sifive/132b0bba-8c44-46f1-b2df-21a886e545eb_sifive-connect-logo-nl.png?auto=compress,format)
SiFive Connect – SiFive in a Virtual World Webinar Series<br>
A platform designed for continued engagement with the global hardware and software community developing RISC-V based semiconductor solutions. These monthly events will take place twice on the same day (9 a.m. PDT and 6 p.m. PDT) to enable convenient participation from a variety of time zones.
[Learn more](https://www.sifive.com/resources/webinars).

Events<br>
SiFive Connect Webinar
![Embedding Intelligence Everywhere](https://images.prismic.io/sifive/02667a10-9df0-478c-9099-7451cbe31b8d_embedding-intelligence-blog-photo.jpg?auto=compress,format)
Embedding Intelligence Everywhere with SiFive 7 Series Core IP<br>
Thursday, April 16<br>
9 am - 10 am PDT<br>
6 pm - 7 pm PDT - [Learn more](https://info.sifive.com/embedding-intelligence-everywhere-with-sifive-7-series-core-ip).

![Rapid Embedded Prototyping with SiFive Software](https://images.prismic.io/sifive/8ced59ef-f22b-4e4a-8aa4-66ee6260d127_rapid-embedded-prototyping-blog-photo.jpg?auto=compress,format)
Rapid Embedded Prototyping with SiFive Software<br>
Thursday, April 30<br>
9 am - 10 am PDT<br>
6 pm - 7 pm PDT - [Learn more](https://info.sifive.com/rapid-embedded-prototyping-with-sifive-software).


![The Linley Group](https://images.prismic.io/sifive/2f7c71bf-2d70-4ba8-a4e1-dab46af9e323_linley-group-logo-nl.png?auto=compress,format)
The Linley Group<br>
SiFive Presented at the Virtual Linley Spring Processor Conference April  6-9:
*The Direction and Magnitude of SiFive Intelligence*, by Nick Knight, Software Performance Team.<br>
[View proceedings](https://www.linleygroup.com/events/index.php).

*Vectors are History: 30 Years Later*, by Randy Allen, VP of RISC-V Software.<br> 
[View proceedings](https://www.linleygroup.com/events/index.php).

![](https://images.prismic.io/sifive/22883c8e-e542-4508-b525-10b3146d04a3_cicc-logo.png?auto=compress,format)
SiFive was a Key Participant in IEEE’s 2020 CICC Forums (Virtual Conference Online) March 23 and March 24: 

Co-Founder and Chief Architect Krste Asanovic presented SiFive: *A Startup with a Mission to Democratize Access to Custom Cores and Silicon*.<br>
[View proceedings](http://ieee-cicc.org/virtual-event-information/).

Chief SoC Architect Shubu Mukherjee presented *Challenges and Solutions for Domain-Specific Custom Silicon*.,<br>
[View proceedings](https://www.sifive.com/resources/webinars/getting-started-with-sifives-soc-ips).

![](https://images.prismic.io/sifive/4f6b0b4d-15d6-4f24-aa86-aa7ce53766c1_embedded-world-logo.png?auto=compress,format)
SiFive was a Key Participant at Embedded World 2020, Nuremberg, Germany (Feb 25-27) – Demonstrated SiFive Core Designer, and SiFive Shield with WorldGuard, which offers core-driven and process-id driven modes for multi-domain security.

![View past proceedings](https://images.prismic.io/sifive/97148612-553e-44e2-908b-854572bf0fce_glimpses-day-2.png?auto=compress,format)

SiFive hosted Tech Symposiums in San José, Costa Rica (co-located with LASCAS 2020), and Mexico City, Mexico in February, and a special two-day symposium and workshop in Ahmedabad, India in early March – The RISC-V ISA is gaining momentum.

Technical Papers
- Check out SiFive Secures RISC-V. [Learn more](https://www.sifive.com/resources/case-studies).
- Check out SiFive U8 TAKES RISC-V OUT OF ORDER. [Learn more](https://www.sifive.com/resources/case-studies).






Making Great Progress on RISC-V IP and Silicon Solutions

Welcome Back!

It’s been a while since our last newsletter - a lot has happened since we last reached out, not the least of which was the release of our latest core IP, the [SiFive S2 Series Core IP](https://www.sifive.com/press/sifive-launches-the-worlds-smallest-commercial-64-bit), which is the world’s smallest 64-bit RISC-V based embedded core. Designed for edge computing loads, the S2 Series further adds to our extensive, vastly customizable, optimized, silicon-proven embedded core IP portfolio.

We’ve also expanded our offerings with a new IP enablement platform in 7 nm FinFET. The tapeout includes critical IP validation of our high bandwidth memory (HBM2E), 3.2 Gbps interface, 2GHz Ternary Content-Addressable Memory (TCAM) partner IP, a low-voltage differential signaling (LVDS) interface and other key IP building blocks.

Interested in trying out our newest releases? Swing by our website and sign up for access to [SiFive Core Designer](https://www.sifive.com/core-designer), which will allow you to access best-in-class SiFive core IP and the tools to customize it to your exact specifications. See what customers like DinoplusAI, Synaptics, Western Digital and others are using to develop their custom SiFive based RISC-V designs. And check out our new
[HiFive1 Rev B](https://www.crowdsupply.com/sifive/hifive1-rev-b?utm_campaign=Newsletter&utm_source=hs_email&utm_medium=email&utm_content=2&_hsenc=p2ANqtz--BUBC4uTuVPsOPS1vQ61L7X8zBEvMa3W3g6aWQDaAFhNSXwCPzChieXW5BBkgNHurLG2j9mT79DEuspEO4DRL_jTDcdA&_hsmi=2) development board, available through CrowdSupply.

New Webinar Series 

Back by popular demand, SiFive Sr. Product Marketing Manager Drew Barbier will give [another series of webinars](https://www.sifive.com/resources/webinars/introducing-risc-v--sifives-2-series-products) aimed at introducing a new audience to RISC-V and SiFive’s products and workflow.
![Webinar Series](https://images.prismic.io/sifive/7eabf0c2-00b2-4059-af83-bdcdbe00a8b4_intro-risc-v-ip-series.jpg?auto=compress,format)

- May 7th, 10:30am PST: An Introduction to the RISC-V Architecture<br>
This webinar will introduce RISC-V Architecture. It will provide an overview of RISC-V Modes, Instructions and Extensions, Control and Status Registers, and Interrupts. It is targeted at embedded developers who are new to RISC-V.

- May 15th, 10:30am PST: SiFive’s 2 Series Core IP<br>
This webinar will introduce SiFive’s 2 Series Core IP, SiFive’s smallest and most efficient RISC-V Processor IP, which is ideal for embedded applications from microcontrollers to control processors to IoT applications. This webinar will cover the 2 Series Core architecture, the configurability of the 2 Series, and the Core Local Interrupt Controller (CLIC).

- May 23rd, 10:30am PST: From a Custom 2 Series Core to Hello World in 30 Minutes <br>
The last webinar will be very hands-on! Drew, the host, will walk through configuring a custom E2 core using SiFive Core Designer, and then use Freedom Studio to write software targeting the custom core in the included RTL testbench and on an FPGA.

Here, There and Everywhere ... 

In addition to all this good news, we’ve also had a lot of really great experiences so far in 2019. We’ve seen so many of our customers and RISC-V enthusiasts at CES, Mobile World Congress, Embedded World and many other conferences. It’s been great to talk with you all about your interest in SiFive’s Core IP and Core Designer. Here’s an update on where we’ve been the past few weeks:

Building on the success We kicked off our global [RISC-V Technical Symposia]() series with sessions in the Bay Area, Boston and Austin to great success, the first of more than 50 planned meetings around the world. The free events are designed to promote the open instruction set architecture and foster deeper collaboration and engagement with the global open-source community. In the coming months, we’ll bring the Symposia to China and Europe. Click the link above to find out where we’ll be next and register to attend a session near you.
![RISC-V Technical Symposia]()

We’ve been busy attending a number of industry events as well. Earlier this month, our CTO and cofounder, Yunsup Lee, spoke on “Extending and Optimizing 64-bit RISC-V Processors” at IP-SOC. Around the same time, our chief engineer and cofounder, Krste Asanovic,  gave a talk during the Linley Spring Processor Conference on customizing RISC-V SoCs for artificial intelligence applications.

Forum Highlight<br>
The [SiFive Forums](https://forums.sifive.com/?utm_campaign=Newsletter&utm_source=hs_email&utm_medium=email&utm_content=2&_hsenc=p2ANqtz--BUBC4uTuVPsOPS1vQ61L7X8zBEvMa3W3g6aWQDaAFhNSXwCPzChieXW5BBkgNHurLG2j9mT79DEuspEO4DRL_jTDcdA&_hsmi=2) are buzzing! They are packed with valuable content that can answer your questions and satisfy your curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that caught our attention (and will now have yours, too!):

- [Will RISC-V avoid the Linux mainlining mess that ARM had?](https://bit.ly/2QUp39y)
- [About benchmark compile environment for E31 evaluation](https://bit.ly/2thP8WZ)
- [Simple keyboard for GPIO](https://bit.ly/2uQrLUT)

SiFive in the Press<br>
Want to see who has been talking about SiFive recently? Let's take a look!<br>
[Synaptics announces shift to RISC-V processors](https://bit.ly/2stDbgy), by Gareth Halfacree, Bit-tech.net<br>
[Start developing for RISC-V with the $49 HiFive1 Revision B](https://tek.io/2tmfpDB), by James Sanders, TechRepublic<br>
[CHIPS Alliance to curate building blocks for RISC-V chips](https://bit.ly/2RjQpES), by Eric Brown, LinuxGizmos<br>
[HiFive1 Rev B wireless open source RISC-V development platform](https://bit.ly/30j7SS6), by Julian Horsey, Geeky Gadgets<br>
[The Linux Foundation announces the CHIPS Alliance project for deeper open source hardware integration](https://bit.ly/388mFlk), by Sugandha Lahoti, Packt<br>
[SiFive Rolls Out RISC-V HiFive1 Rev B Development Platform, $49 USD With FE310-G002 SoC](https://bit.ly/384DVb0), by Michael Larabel, Phoronix<br>

RISC-V in the News<br>
We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

[8 RISC-V Companies to Watch](https://ubm.io/2NtQG77) by Christopher Wiltz, Design News<br>
[5 Key Takeaways from the RISC-V Roadshow in Boston](https://bit.ly/2To6w6Z), by Dan Mandell, VDC Research<br>
[Multi-core, Linux-ready RISC-V cores feature DSP](https://bit.ly/2uNmi0Z), by Eric Brown, LinuxGizmos<br>
[Calista Redmond named CEO of RISC-V Foundation](https://bit.ly/2tah3rY), by Staff, InsideHPC<br>
[Linux Foundation launches FOSSi-focused CHIPS Alliance](https://bit.ly/35Qdvbr), by Gareth Halfacree, Bit-tech<br>
[RISC-V Foundation Hosting Worldwide Series of Getting Started with RISC-V Events](https://bit.ly/36VhvZE), by Gary Elinoff, All About Circuits<br>
[5 Key Takeaways from the RISC-V Roadshow in Boston](https://bit.ly/3a7awyK), by Dan Mandell, VDC Research<br>

We would love to hear from you - reply to this email with any questions or inquiries, and we will get right back to you!

Thanks for your continued support!

Until next time,<br>
Jack and the team at SiFive

PS - if you are getting this message forwarded to you, and want to sign up for future newsletters, you can do so [here](https://bit.ly/36VkSji)


It’s been a while since our last newsletter - a lot has happened since we last reached out, not the least of which was the release of our latest core IP

Welcome Back!

It’s been a while since our last newsletter - a lot has happened since we last reached out.
2019 was another impressive year for SiFive. We made great strides in multiple areas, such as bookings, revenue, team size, number of locations around the world, and capital that we have raised

However, the most wonderful thing about 2019 was the number of customers, investors, DesignShare partners, and university partners that we worked with throughout the year - over 120 organizations. We appreciate all of you for making SiFive what it is today!

Wishing everyone a happy and prosperous 2020!

Naveed Sherwani<br>
President & CEO<br>
SiFive, Inc.

Here, There and Everywhere ...<br>
[SiFive Completes its Global 52-City Tech Symposium/Workshop Tour](https://bit.ly/2NTc6e4) 
![52 City Global](https://images.prismic.io/sifive/ad5a3bc3-92d3-4042-84da-b76a864a0086_lahore-symposium.png?auto=compress,format)
The RISC-V ISA is rapidly becoming the new standard for compute and has literally spawned a worldwide revolution in the semiconductor industry. At the beginning of 2019, SiFive set out to foster education about its RISC-V based technologies and to advance deeper collaboration within the global hardware community. We succeeded! We completed 52 Tech Symposiums/Workshops reaching 26 countries and six continents – reaching all corners of the world. Over 10,000 people attended these events, demonstrating strong attraction to RISC-V in not only industry, but in academia as well.

[SiFive Attended CES 2020](https://bit.ly/2tEJcYr)

SiFive deepens AI portfolio with strategic new disclosures at CES 2020, unleashing semiconductor product roadmaps for consumer and commercial SoCs.

- [SiFive and Ceva Partner To Build Mainstream Edge AI Processors](https://bit.ly/37pVrXn)
- [RISC-V business: SiFive and CEVA join forces to enable the development AI- amenable, edge-oriented processors](https://bit.ly/2GkzBZh)
- [CES Unveiled: Know Thyself, Groom Thyself](https://ubm.io/30SxAx1)
- [CES Unveiled Tech for a better Society/](https://bit.ly/2TVDjRk)[What’s new at CES 2020](https://bit.ly/30SzvBJ)
- [Week In Review: IoT, Security, Autos](https://bit.ly/38NOHTB)

[SiFive Presented New Technologies at RISC-V Summit 2019](https://bit.ly/38yufWk)<br>
At the 2019 RISC-V Summit there were more than 1,670 registrants – that’s 500 more attendees compared to the event last year, showing how the RISC-V ecosystem is continuing to rapidly grow. View proceedings to learn key takeaways.

[Samsung to use SiFive RISC-V Cores for SoCs, Automotive, 5G Applications](https://bit.ly/30SAa6b)<br>
At the annual RISC-V Summit, Samsung disclosed the use of SiFive’s RISC-V cores for upcoming chips for a variety of applications.

[RISC-V grows globally as an alternative to Arm and its license fees](https://bit.ly/2GnRB4Z)<br>
[RISC-V Xmas gifts: SiFive Emits Vector Enabled Cores](https://bit.ly/2TV5xeI)<br>
[SiFive Celebrates Historic 100 Design Win Milestone](https://bit.ly/38AfC4Y)<br> 
[SiFive Wins Elektra Award 2019](https://bit.ly/36tjKlH)

![GSA Award](https://images.prismic.io/sifive/e38e70b4-6eca-42ce-95fb-00dda8dfa88e_GSA-awad-SiFive-team.png?auto=compress,format)<br>
[SiFive Retains Title of Most Respected Private Semiconductor Company](https://bit.ly/2GrlktL)
RISC-V leader honored for second consecutive year for its hyper growth, products and performance by the Global Semiconductor Alliance.

In 2019, SiFive reached another milestone with the shipment of 150 million ASICs to date

Product Highlights<br>
[SiFive Announces New Technologies for Mission-Critical and AI Markets](https://bit.ly/2uuYIGl)<br>
[SiFive Learn Inventor Development System Now AWS Qualified](https://bit.ly/37qhP2H)<br>
[SiFive Announces SiFive Learn Initiative](https://bit.ly/2NUBCji)<br>
[SiFive Announces New U8-Series Core IP for High-Performance Compute](https://bit.ly/36o5lY4)<br>
[SiFive Announces New SiFive Shield for Modern SoC Design](https://bit.ly/3aIbAcA)

New Partnerships<br>
[SiFive and CEVA Partner to Bring Machine Learning Processors to Mainstream Markets](https://bit.ly/2tOnjpw)<br>
[Breker RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis](https://bit.ly/2GiZo48)<br>
[Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors](https://bit.ly/2uyZsde)<br>
[Wind River Announces RISC-V Support for VxWorks RTOS](https://bit.ly/2GkjIST)

[Upcoming Events](https://www.sifive.com/events)<br>
![Events](https://images.prismic.io/sifive/93180f58-be7a-44e9-803a-dd9ea18872b3_event-date-series.png?auto=compress,format)

We would love to hear from you - reply to this [email](mailto:info@sifive.com) with any questions or inquiries and we will get right back to you!

Thanks for your continued support!

Until next time,<br>
The team at SiFive

PS - if you are getting this message forwarded to you, and want to sign up for future newsletters, you can do so [here](https://bit.ly/36VkSji)


Wrapped Up a Great Year – Leading the RISC-V Momentum

We recently [announced](https://www.sifive.com/posts/2018/05/08/intel-capital-event/) that Intel Capital participated in our Series C funding round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at the Intel Capital Global Summit. 

The investment comes at a pivotal time as we cement our vision for the future. As you know, our goal is to leverage the body of software and tools available from the open-source community with the intention of dramatically reducing the cost of developing custom silicon. But you may be wondering what this really looks like…

We aim to get silicon in the hands of designers as quickly as possible. Let them take a test drive to run benchmarks and discover where the chip works well for an intended purpose, and then form a plan for when and how to move it into full-scale production. The hope is that this process supports all types of companies, including startups who otherwise might have to design around off-the-shelf silicon.

With our recent funding, including the Intel Capital investment, we look forward to making this a reality and continue leading the RISC-V revolution.

### Ready For Take Off!
In addition to all of the good news, we’ve also had a lot of really great experiences over the past month. Here’s a snapshot of where we’ve been:

<div><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/Barcelona_Yunsup%20L.jpg?t=1527187686911" alt="Barcelona Yunsup" /></div>
 
To start the journey, we headed to Barcelona for some paella and the latest [RISC-V Workshop](https://www.sifive.com/posts/2018/05/02/sifive-to-discuss-latest-technology-developments-at-risc-v-workshop/).  Andrew Waterman, Krste Asanovic, Palmer Dabbelt and Yunsup Lee led a total of five sessions, which included a demo of the full-featured Debian Linux Distribution running on HiFive Unleashed.

Next up was the [Intel Capital Global Summit](https://www.intelportfolio.com/globalsummit/) in Palm Desert where Naveed received the “Elevator Pitch Award” and announced the investment from Intel Capital.

Then, we hopped a flight to Shanghai for the GSA Symposium and our own [2018 Technical Symposium](https://www.sifive.com/posts/2018/05/15/sifive-to-hold-inaugural-technical-symposium-in-shanghai/) where we provided an overview of the RISC-V ISA, our history and future trends, as well as demonstrations from our executives and partners.

### Featured Developer
Our view of the world centers around the developer, the engineer, the user, the dreamer. It’s you who are contributing to RISC-V and open-source, which makes what we do at SiFive possible.

We’d like to give a shout to Microsemi for collaborating with us on the [HiFive Unleashed Expansion Board](https://www.prnewswire.com/news-releases/microsemi-and-sifive-launch-hifive-unleashed-expansion-board-enabling-linux-software-and-firmware-developers-to-build-risc-v-pcs-for-the-first-time-300642936.html). It is an exciting time in the RISC-V revolution, and our work together to reach the broader Linux market is another landmark.

Upgrading the HiFive Unleashed board allows developers to add custom peripherals to the board via PCIe, USB and other connections. The Expansion Board will be available for a limited time only at the cost of $1,999, or you can get the HiFive Unleashed and the Expansion Board as a bundle of $2,998.

Are you working on something interesting? We’d love to feature you next. Drop by and [let us know](mailto:info@sifive.com) what you are working on!

Forum Highlight
The [SiFive Forums](https://forums.sifive.com/) are buzzing! They are packed with valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that caught our attention (and will now have yours, too!).

- [HiFive1 SPI Question?](https://forums.sifive.com/t/hifive1-spi-question/1226)
- [Generate an accurate 50Hz waveform](https://forums.sifive.com/t/generate-an-accurate-50hz-waveform/1220)
- [Unsupported DTM Version](https://forums.sifive.com/t/unsupported-dtm-version/990)

### SiFive in the Press 
Want to see who has been talking about SiFive recently? Let’s take a look!

[SiFive Releases ‘Expansion Board’ to Build Interest in RISC-V Processor](http://www.datacenterknowledge.com/hardware/sifive-releases-expansion-board-build-interest-risc-v-processor) by Christine Hall, Data Center Knowledge

[HiFive-Unleashed Expansion Board Opens Door for RISC-V PCs](https://www.designnews.com/electronics-test/hifive-unleashed-expansion-board-opens-door-risc-v-pcs/183342268658749) by Chris Wiltz, Design News

[Expansion Board Enhances Popular RISC-V Development Board](https://www.sensorsmag.com/embedded/expansion-board-enhances-popular-risc-v-development-board) by Mathew Dirjish, Sensors Magazine

[RISC-V expansion board for Linux software and firmware developers](http://www.eenewseurope.com/news/risc-v-expansion-board-linux-software-and-firmware-developers) by Julien Happich, eeNews Europe

[Intel Capital invests in RISC-V start-up SiFive](https://www.sensorsmag.com/embedded/expansion-board-enhances-popular-risc-v-development-board) by Gareth Halfacree, Bit-tech.net

[Intel Capital invests $72M in startups, including 7 from the Bay Area](https://www.bizjournals.com/sanjose/news/2018/05/08/intel-capital-invests-72m-in-startups-including-7.html) by Cromwell Schubarth, Silicon Valley Business Journal

[SiFive’s Design Democratization Drive](https://www.semiwiki.com/forum/content/7416-sifive-s-design-democratization-drive.html) by Camille Kokozaki, SemiWiki.com

### RISC-V in the News
We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

[Thales to launch RISC-V into space applications](http://www.eenewseurope.com/news/thales-launch-risc-v-space-applications-0) by Peter Clarke, eeNews Europe

[RISC-V processors make play for AI in Barcelona, says Esperanto](https://www.electronicsweekly.com/news/risc-v-processors-make-play-ai-barcelona-says-esperanto-2018-05/) by Richard Wilson, ElectronicsWeekly.com

[Low-Power Play: GAP8 Weds Multicore RISC-V with Machine Learning](http://www.electronicdesign.com/embedded-revolution/low-power-play-gap8-weds-multicore-risc-v-machine-learning) by William Wong, Electronic Design

[Brains behind seL4 secure microkernel begin RISC-V chip port](https://www.theregister.co.uk/2018/04/23/risc_v_sel4_port/) by Richard Chirgwin, The Register

[Andes adopts UltraSoC](https://www.electronicsweekly.com/news/business/andes-adopts-ultrasoc-2018-04/) by David Manners, ElectronicsWeekly.com

[Rambus picks RISC-V for new crypto chip](https://www.bit-tech.net/news/rambus-picks-risc-v-for-new-crypto-chip/1/) by Gareth Halfacree, Bit-tech.net

We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!

Thanks for your continued support!  
Until next time,  
Jack Kang

 

PS - if you are getting this message forwarded to you, and want to sign up for future newsletters, you can do so [here](https://info.sifive.com/sifive-newsletter-signup)

We recently announced that Intel Capital participated in our Series C funding round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at the Intel Capital Global Summit. The investment comes at a pivotal time as we cement our vision for the future.

We’re heading to the [Embedded Linux Conference](https://events.linuxfoundation.org/events/elc-openiot-north-america-2018/features-and-add-ons/co-located-events/) next week, March 12-14, to hold our first [hackathon](https://www.sifive.com/posts/2018/02/26/sifive-to-host-risc-v-hackathon-at-embedded-linux-conference/). Developers will be among the first to run code on the HiFive Unleashed board with a chance to take home a board of their own and win a $1,000 cash prize. 

Wondering what you’ll need to bring with you?

We’ll provide 50 HiFive1 and 50 HiFive Unleashed boards along with the associated power supplies, USB cables and SD cards. You’ll need to bring your own computer that’s capable of running your preferred development environment.

<div><img alt="HiFive Unleashed" src="https://cdn2.hubspot.net/hub/3020607/hubfs/HiFive_Unleashed_Angle_2-1.jpg" /></div>

Good news, the Hackathon is free for conference attendees! [Register here](https://www.regonline.com/registration/Checkin.aspx?EventID=2112952); and if you haven’t already, check out Palmer Dabbelt’s latest in the [All Aboard](https://www.sifive.com/blog/2018/03/03/all-aboard-part-11-risc-v-hackathon-presented-by-sifive/) series to learn more about the Hackathon challenges.

### We’re Growing in More Ways Than One!
Speaking of the HiFive Unleashed, SiFive demonstrated the first real-world use of the board at FOSDEM in February, highlighting the launch of the board, which features the industry’s only Linux-capable RISC-V based processor SoC.

What an exciting time for us and the open-source community!

Developers can purchase the HiFive Unleashed board [online](https://www.sifive.com/products/hifive-unleashed/). The board will ship in late March for early access users with more boards shipping in late June.

It’s been a busy few months for us as we’ve also been working to grow our team. Join us in welcoming two industry all-stars:

- [Shafy Eltoukhy](https://www.sifive.com/posts/2018/01/30/custom-silicon-veteran-joins-sifive-executive-team/), who joins us as VP of operations, will lead our DesignShare program. Shafy comes to SiFive with three decades of experience, most recently as VP and business unit manager for the analog mixed signal division at Microsemi.
- [Shiva Natarajan](https://www.sifive.com/posts/2018/02/14/sifive-appoints-cfo-to-executive-team/) who is our newly appointed CFO, will structure and oversee company growth. Previously, Shiva was VP of finance at A10 Networks.  

Interested in being part of the revolution? Want to help democratize access to custom, state-of-the-art chips? [Join us](https://www.sifive.com/about/jobs/)!

### Featured Developer
Our view of the world centers around the developer, the engineer, the user, the dreamer. It’s you who are contributing to RISC-V and open-source, making what we do at SiFive possible.

<div><img alt="DAgema Tesla Coils" src="https://cdn2.hubspot.net/hub/3020607/hubfs/DAgema_Tesla_Coils.jpg" /></div>

The developer we’re featuring today is Donnie Agema, known as “dagema” on our forums. He’s currently studying Computer Organization and Design to better enable him to learn the RISC-V ISA, using our HiFive1 board and the Arty platform for hands-on training. This photo to the left is one of the projects he’s working on, showing two Tesla coils getting in touch with one another.

We asked Donnie how he discovered SiFive, and his response:

“Electronics has been my hobby since childhood, beginning in the vacuum tube era. But my early career as logistics manager and later as SAP systems engineer put that hobby on the back burner for many years. When I began approaching retirement age, I decided to start reviving my lifelong hobby, and found I had been left behind by the onslaught of microprocessors.

After retirement, I am now trying to get back up to speed, which means learning all about microprocessors. Having the desire to start at the bottom and work my way up, it seemed to me that the near future was in RISC-V and FPGAs. That combination brought me to the SiFive website, of which I have become an avid follower.”

Thanks for being a fan, Donnie!  We look forward to seeing more of your projects.

Are you working on something interesting? We’d love to feature you next. Drop us a line and [let us know](mailto:info@sifive.com) what you are working on!

### Forum Highlight
The SiFive Forums are buzzing! They are packed with valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that caught our attention (and will now have yours, too!):

- [Tilelink](https://forums.sifive.com/t/tilelink/1032)
- [Freedom e300 on Kintex 7 KC705 Evaluation Kit](https://forums.sifive.com/t/freedom-e300-on-kintex-7-kc705-evaluation-kit/1026)
- [OpenOCD JTAG](https://forums.sifive.com/t/openocd-jtag/195)

### Blog Posts
What’s been on our minds, you ask? Quite a few things, but here are some blog highlights over the past month including Palmer’s latest on the All Aboard series:

[All Aboard, Part 11: RISC-V Hackathon, Presented by SiFive](https://www.sifive.com/blog/2018/03/03/all-aboard-part-11-risc-v-hackathon-presented-by-sifive/) by Palmer Dabbelt

[All Aboard, Part 10: How to Contribute to the RISC-V Software Ecosystem](https://www.sifive.com/blog/2018/02/20/all-aboard-part-10-how-to-contribute-to-the-risc-v-software-ecosystem/) by Palmer Dabbelt

[Welcome Aboard, Sunil Shenoy!](https://www.sifive.com/blog/2018/03/01/welcome-aboard-sunil-shenoy/) by Allen Leibovitch

### SiFive in the Press
Want to see who has been talking about SiFive recently? Let’s take a look!

[Moore’s Law is Dead: So, Let’s Talk About the Future of SoCs](https://www.sensorsmag.com/components/moore-s-law-dead-so-let-s-talk-about-future-socs) by Jack Kang, VP of product and business development, SiFive, Sensors Magazine

[Paul Kocher: Differential Power Analysis And Spectre](https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/kocher) by Paul McLellan, Breakfast Bytes Blog, Cadence Community

[First Open-Source RISC-V SoC For Linux Released](https://www.designnews.com/electronics-test/first-open-source-risc-v-soc-linux-released/86012081658262) by Chris Wiltz, Design News

[Is Open Source RISC-V Ready To Take On Intel, AMD, And ARM In The Data Center?](http://www.datacenterknowledge.com/hardware/open-source-risc-v-ready-take-intel-amd-and-arm-data-center) By Christine Hall, Data Center Knowledge

[HiFive Unleashed: The First Linux-Capable RISC-V Single Board Computer Is Here](https://www.techrepublic.com/article/hi-five-unleashed-the-first-linux-capable-risc-v-single-board-computer-is-here/) by James Sanders, TechRepublic

[Igniting The Open Hardware Ecosystem with RISC-V - SiFive’s Freedom U500 Is The World’s First Linux-Capable Open Source SoC Platform](https://fosdem.org/2018/interviews/palmer-dabbelt/), FOSDEM Interviews

[Intel’s Sunil Shenoy Joins RISC-V Start-Up SiFive](http://www.bit-tech.net/news/tech/cpus/intels-sunil-shenoy-joins-risc-v-start-up-sifive/1/) by Gareth Halfacree, Bit-tech.net

[SiFive Introduces RISC-V Linux-Capable Multicore Processor](https://hackaday.com/2018/02/03/sifive-introduces-risc-v-linux-capable-multicore-processor/) by Brian Benchoff, Hackada

### RISC-V in the News
We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

[A New Era Of Storage: Open Compute With RISC-V And Memory Fabrics](http://www.embedded-computing.com/hardware/a-new-era-of-storage-open-compute-with-risc-v-and-memory-fabrics) by Dr. Zvonimir Bandic, Western Digital, Embedded Computing Design

[11 Myths About The RISC-V ISA](http://www.embedded-computing.com/hardware/a-new-era-of-storage-open-compute-with-risc-v-and-memory-fabrics) by Ted Marena, director of SoC/FPGA products, Microsemi, Electronic Design

[RISC-V Processor Mr Wolf Arrives To Solve Problems](http://www.eenewseurope.com/news/risc-v-processor-mr-wolf-arrives-solve-problems) by Peter Clarke, eeNews Europe

[RISC-V Processor Trace IP An Industry First](https://www.sensorsmag.com/components/risc-v-processor-trace-ip-industry-first) by Mathew Dirjish, Sensors Magazine

[RISC-V Processor Trace IP Available](https://www.electronicsweekly.com/news/design/eda-and-ip/risc-v-processor-trace-ip-available-2018-01/) by Steve Bush, ElectronicsWeekly.com

[Nvidia, Western Digital At Chips’ Frontier](https://www.barrons.com/articles/nvidia-western-digital-at-chips-frontier-1516640945) by Tiernan Ray, Barron’s

Thanks for your continued support!  
Until next time,  
Jack Kang

_We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!_

At the Embedded Linux Conference we're holding our first hackathon. Developers will be among the first to run code on the HiFive Unleashed board with a chance to take home a board of their own and win a $1,000 cash prize.

Before we dive into our newsletter, we want to take a moment to talk about the vulnerabilities around Meltdown and Spectre. First off -- and most fortunately -- SiFive’s RISC-V Core IP offerings are [not affected by Meltdown and Spectre](https://www.sifive.com/blog/2018/01/05/sifive-statement-on-meltdown-and-spectre/). Secondly, as the [RISC-V Foundation’s statement](https://riscv.org/2018/01/more-secure-world-risc-v-isa/) on these vulnerabilities notes, now is the time for open architecture and open hardware designs to shine.

Now, on to the fun stuff.

We wrapped up our “Getting Started with SiFive IP” webinar series last week. The three-part series covered everything from instruction types and modes to using evaluation versions of our E31 and E51 Core IPs. Missed a webinar? No sweat -- we have you covered. Check out [the recordings to all three sessions here](https://info.sifive.com/risc-v-webinar). 

Last, but certainly not least, we were fortunate enough to [welcome Sunil Shenoy](https://www.sifive.com/posts/2018/01/22/sifive-welcomes-former-intel-corporate-vp-to-executive-team/), former corporate VP at Intel, to the growing SiFive team as vice president of hardware engineering. Sunil brings more than 30 years of technology experience to SiFive, from holding 16 patents in microprocessor design to leading multi-national teams of thousands of engineers. We’re thrilled to have him on board and expanding our mission to simplify access to customizable RISC-V Core IP!

### All Aboard: An Update on RISC-V

<div><img alt="All Aboard logo" src="https://cdn2.hubspot.net/hub/3020607/hubfs/All%20Aboard%20logo%20(1).jpg?t=1516735118340" /></div>

Since the Workshop, Palmer’s been furiously covering the RISC-V ecosystem. Here are some of his recent thoughts:

- [All Aboard, Part 8: The RISC-V Linux Port is Upstream!](https://www.sifive.com/blog/2017/12/05/all-aboard-part-8-the-risc-v-linux-port-is-upstream/)
- [All Aboard, Part 9: Paging and the MMU in the RISC-V Linux Kernel](https://www.sifive.com/blog/2017/12/11/all-aboard-part-9-paging-and-mmu-in-risc-v-linux-kernel/)

Are you interested in being a part of the evolution? [Let’s talk](https://www.sifive.com/about/contact/)!

### Upcoming Events
We’re headed to Brussels for the upcoming FOSDEM 2018 event! Our very own Palmer Dabbelt will be speaking on Saturday, Feb. 3. His panel, titled “[Igniting the Open Hardware Ecosystem with RISC-V](https://fosdem.org/2018/schedule/event/riscv/),” will explore the RISC-V ISA, the Rocket Chip processor generator and the state of RISC-V.

Embedded World is also coming up in Nuremberg, and we’ve teamed up with the RISC-V Foundation to sponsor a “passport” program where attendees can visit multiple RISC-V member companies at the show and have a chance to win a HiFive1 board. 

### Featured Developer
Our view of the world centers around the developer, the engineer, the user, the dreamer. It’s you who are contributing to RISC-V and open-source, making what we would do at SiFive possible.

<div><img alt="fRISCy" src="https://cdn2.hubspot.net/hub/3020607/hubfs/fRISCy.png?t=1516735118340" /></div>

This month’s featured developer is Stephen Newberry. Stephen is a hardware engineer who is passionate about PCB design and VHDL. Pursuing his curiosity around RISC-V and programmable logic, Stephen began working on a board based on the SiFive [FE310](https://www.sifive.com/products/freedom-e310/) and a Xilinx Artix-7 FPGA. Named [fRISCy](http://shielddigitaldesign.com/friscy/) (for FPGA + RISC-V), he hopes the board would be suitable for development and inclusion in industrial embedded systems. We are eagerly following Stephen’s progress on the fRISCy via the SiFive [forums](https://forums.sifive.com/) and will be excited to see the prototype.

Some of fRISCy’s key features include:

- SiFive FE310 RISC-V Microcontroller (system controller) with 128Mbit QSPI Flash memory
- Xilinx Artix-7 FPGA with SYZYGY Standard carrier-side connector (footprint compatible from XC7A15T to XC7A100T)
- Raspberry Pi form factor and connector placement, including 40-pin GPIO header, RJ-45, and USB Micro-B
- 10/100 Ethernet PHY and 4Mbit SRAM connected via FPGA
- SPI + GPIO interface between FE310 and FPGA for bidirectional data transfer
- FDTI and UART interfaces

We’d love to feature your SiFive project in the next newsletter - [let us know](mailto:info@sifive.com) what you are working on! 

### Forum Highlights
The [SiFive Forums](https://forums.sifive.com/) are buzzing! They are packed with valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that caught our attention (and will now have yours, too!):

- [Makefile Targeting Scratchpad](https://forums.sifive.com/t/makefile-targeting-scratchpad/924)
- [Low output voltage?](https://forums.sifive.com/t/low-output-voltage/269)
- [Programming the FE310 Program Flash - SPI FLASH Chip Select](https://forums.sifive.com/t/programming-the-fe310-program-flash-spi-flash-chip-select/972)

### More Blog Posts
What’s been on our minds, you ask? Quite a few things, but here are some of our top blogs over the past month:

[RISC-V QEMU Part 1: Privileged ISA v1.10, HiFive1 and VirtIO](https://www.sifive.com/blog/2017/12/20/risc-v-qemu-part-1-privileged-isa-hifive1-virtio/) by Michael Clark

[A Look Back: 7th RISC-V Workshop](https://www.sifive.com/blog/2018/01/03/a-look-back-7th-risc-v-workshop/) by Allen Leibovitch

[SiFive Statement on Meltdown and Spectre](https://www.sifive.com/blog/2018/01/05/sifive-statement-on-meltdown-and-spectre/) by Andrew Waterman  

### SiFive in the Press
Want to see who has been talking about SiFive recently? Let’s take a look!

[The Bisquick Alternative](https://www.eejournal.com/article/the-bisquick-alternative/) by Jim Turley, EE Journal

[Getting Started with RISC-V](https://www.semiwiki.com/forum/content/7225-getting-started-risc-v.html) by Daniel Nenni, SemiWiki.com

[THE SPARK GAP PODCAST - EPISODE 52](http://thesparkgap.net/the-spark-gap-podcast-episode-52/) by The Spark Gap Podcast

[Year in Review: IP Suppliers Take More RISC-V](http://www.linleygroup.com/newsletters/newsletter_detail.php?num=5801) by Mike Demler, The Linley Group

[8 Top Innovations of 2017](https://www.eetimes.com/document.asp?_mc=RSS_EET_EDT&doc_id=1332783&page_number=4) by Rick Merritt, EE Times

[Engineer Spotlight: Shafy Eltoukhy, Head of SiFive’s DesignShare Program](https://www.allaboutcircuits.com/news/engineer-spotlight-head-SifFves-Designshare-program-shafy-eltoukhy/) by Chantelle Dubois, AllAboutCircuits.com

[SiFive, Microsemi Collaborate on RISC-V Development](https://www.pddnet.com/news/2017/12/sifive-microsemi-collaborate-risc-v-development) by Megan Crouse, Product Design & Development

### RISC-V in the News
We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

[Western Dig, Nvidia On Board with ‘RISC-V,’ So Pay Attention, Says Benchmark](https://www.barrons.com/articles/western-dig-nvidia-on-board-with-risc-v-so-pay-attention-says-benchmark-1515001875) by Tiernan Ray, Barron’s

[The Jenga Conundrum](http://www.eejournal.com/article/the-jenga-conundrum/) by Jim Turley, EE Journal

[Western Digital to Use RISC-V for Controllers, Processors, Purpose-Built Platforms](https://www.anandtech.com/show/12133/western-digital-to-develop-and-use-risc-v-for-controllers) by Anton Shilov, AnandTech

[RISC-V Enables Smart Storage Devices](https://www.forbes.com/sites/tomcoughlin/2017/12/01/risc-v-enables-smart-storage-devices/) by Tom Coughlin, Forbes

[Western Digital Gives A Billion Unit Boost To Open Source RISC-V CPU](https://www.forbes.com/sites/tiriasresearch/2017/12/06/western-digital-gives-a-billion-unit-boost-to-open-source-risc-v-cpu/) by Kevin Krewell, Forbes

[The Rise of RISC-V on Display at Workshop](http://www.electronicdesign.com/industrial-automation/rise-risc-v-display-workshop) by William Wong, Electronic Design

[Western Digital Transitions to RISC-V Open-Source Architecture for Big Data, IoT](https://www.designnews.com/electronics-test/western-digital-transitions-risc-v-open-source-architecture-big-data-iot/96736693957917) by Chris Wiltz, Design News

Thanks for your continued support!  
Until next time,  
Jack Kang

_We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!_

SiFive’s RISC-V Core IP offerings are not affected by the Meltdown and Spectre vulnerabilities. Now is the time for open architecture and open hardware designs to shine.

Ringing in 2018 with Fresh Faces and Big Resolutions

First, we are thrilled to have recently [announced](https://www.sifive.com/posts/2018/04/02/sifive-secures-50-million-funding-to-advance-risc-v-based-semiconductors/) that we raised $50.6 million in our Series C funding round! We wanted to thank our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement, so we held a party to celebrate!

![Yunsup Brings First Wafers Home](https://lh6.googleusercontent.com/E24eWXK4qR-pLmjHJwD6fDzc3aFxTqVEaERyz-r3QU-pdHD6K3OFbXFLUHMfR4n7UIZovOBrDWua8qqsAtia9WiSDjzg43QH9RPcizZ8sIQMh_HX4GAbM9MXTeoRrzqhAoLty2dN)

More than 200 SiFivers, investors, partners, customers and spouses turned out in their finest to celebrate our funding round, and the progress we’ve made since our public launch less than two years ago. Several SiFive and industry speakers, including Turing Award winner David Patterson, were on hand to talk about RISC-V adoption and the revolution SiFive is cementing in the industry. Our favorite moment, though,  was when one of our co-founders recalled bringing the first batch of Freedom Everywhere wafers back from Taiwan. (TL;DR - the box got its own seat on the plane.)

We’ve shared a few photos from the evening’s festivities here, and you can find the whole album on the [SiFive Facebook page](https://www.facebook.com/SiFive/).

<table>
<tbody>
<tr>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/camera%20demo.jpg?t=1523895941150" alt="camera demo" /></td>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/patterson.jpg?t=1523895941150" alt="patterson" /></td>
</tr>
<tr>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/dinner.jpg?t=1523895941150" alt="dinner" /></td>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/naveed.jpg?t=1523895941150" alt="naveed" /></td>
</tr>
</tbody>
</table>

### Three Cheers for Our Very Own Turing Award Winner!
At the SiFive Unleashed event, we had the opportunity to congratulate one of our most trusted advisors, David Patterson, who – along with his longtime collaborator John Hennessey – was named a recipient of the 2017 Association for Computing Machinery’s (ACM) A.M. Turing Award for his work in developing a new approach to designing fast, low-power, reduced instruction set computer microprocessors – a.k.a. RISC processors! Being named a Turing laureate is among the highest honors in the industry, and it recognizes lifetime achievement in advancing the course of computing. 

Patterson’s work with RISC dates back to the early 1980s, when his UC Berkeley team developed its first RISC-I processor. That prototype contained a relatively small 44,000 transistors, and outperformed a more conventional CISC design with more than twice as many transistors. Flash forward to today, where RISC-V based SoCs like those based on SiFive core IP are fundamentally changing the semiconductor industry. Quite literally, we wouldn’t be doing the landmark work we’re conducting at SiFive without Dave’s contributions. Congratulations, Dave! Cheers!

### Busy, Busy, Busy...
But we haven’t just been partying it up - we’ve been staying busy here, and there is no rest on the horizon! This spring is jam-packed with events - here are a few of the many places SiFive will be over the next few weeks.

Catch SiFive co-founder Yunsup Lee at [Cool Chips](http://www.coolchips.org/2018/?page_id=11) in Yokohama, Japan, this week, where he’ll talk about how RISC-V is revolutionizing hardware. And on April 19, we’re a sponsor of the [GSA Silicon Summit](https://www.gsaglobal.org/2018ss/) where SiFive CEO Naveed Sherwani will speak.

We’ve also scheduled the next SiFive TechTalk. Krste Asanovic plans to speak about the latest developments in using RISC-V for artificial intelligence at the April 25 event, which will be held at 282 Almaden Blvd in San Jose. Register to [attend here](https://www.eventbrite.com/e/sifive-tech-talk-on-accelerating-ai-past-present-and-future-tickets-45089030504)!

A group of us will also participate in the TSMC 2018 Technology Symposium, which will take place the first few weeks in May and hit Santa Clara, Calif.; Austin, Texas; and Boston. You won’t want to miss out - [register today](https://www.regexpo.com/tsmc/symposium18/index.asp?varEvent=2018_SNA_A)!

### Featured Developer
Our view of the world centers around the developer, the engineer, the user, the dreamer. It’s you who are contributing to RISC-V and open-source, making what we do at SiFive possible. Last month, we held our first [Hackathon](https://www.sifive.com/blog/2018/03/03/all-aboard-part-11-risc-v-hackathon-presented-by-sifive/) at the Embedded Linux Conference and we’d like to give a huge shout out to the winners: Hasan, Moritz, Trung and Matt!

Curious what these four had to accomplish for the big cash prize and HiFive Unleashed board? Here are the  highlights:

<div><img src="https://lh5.googleusercontent.com/xIqoo72n_IWBL4wvNBBp5AuxInRMZEl_WBlgo1V0v3RhwWONVT6eEFpP7X0LvlkRGoS2akOi4LEhhIz1EIl3ZwXf1_IaXd_pOt-bTN9Fi2flv9LjaJHpnc7Skhai4f2yCoZLkhCZ" /></div>

- Hasan won the embedded contest by getting a USB sync packet to transfer between the HiFive1 and the host over HiFive1's GPIO pins.
- Matt won the JavaScript contest with his port of Spider Monkey to RISC-V; he then ran the Sun Spider benchmark on a HiFive Unleashed board.
- Moritz and Trung won the open contest with a port of OpenEmbedded to a HiFive Unleashed board.

Thanks to all who participated for your dedication to SiFive and the open-source RISC-V community. Can’t wait for the next hackathon!

Are you working on something interesting? We’d love to feature you next. Drop by and [let us know](mailto:info@sifive.com) what you are working on!

### Forum Highlight
The [SiFive Forums](https://forums.sifive.com/) are buzzing! They are packed with valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that caught our attention (and will now have yours, too!):

- [Initial OTP programming of FE310 chips](https://forums.sifive.com/t/initial-otp-programming-of-fe310-chips/1131)
- [HiFive Unleashed Linux kernel port?](https://forums.sifive.com/t/hifive-unleashed-linux-kernel-port/1094)
- [Bare-metal anyone?](https://forums.sifive.com/t/bare-metal-anyone/407)

### SiFive in the Press
Want to see who has been talking about SiFive recently? Let’s take a look!

[SiFive gets $50.6M to help companies get their custom chip designs out the door](https://techcrunch.com/2018/04/02/sifive-gets-50-6m-to-help-companies-get-their-custom-chip-designs-out-the-door/) by Matthew Lynley, TechCrunch

[SiFive raises $50.6 million for licensable custom microprocessors](https://venturebeat.com/2018/04/02/sifive-raises-50-6-million-for-licensable-custom-microprocessors/) by Dean Takahashi, VentureBeat

[SiFive Raises $50.6 Million to Recreate Chip Prototyping](http://www.electronicdesign.com/embedded-revolution/sifive-raises-506-million-recreate-chip-prototyping) by James Morra, Electronic Design

[RISC-V Silicon Startup Raises $50.6 Million and Inks Western Digital Deal](http://www.datacenterknowledge.com/hardware/risc-v-silicon-startup-raises-506-million-and-inks-western-digital-deal) by Christine Hall, Data Center Knowledge

[SiFive Preps RISC-V Cloud Service](https://www.eetimes.com/document.asp?doc_id=133314) by Rick Merritt, EE Times

[RISC-V leader gains $50 million in funding and Western Digital vows to build 1 billion chips](http://linuxgizmos.com/risc-v-leader-gains-50-million-in-funding-and-western-digital-vows-to-build-1-billion-chips/) by Eric Brown, LinuxGizmos.com

### RISC-V in the News
We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

[RISC-V Stands To Gain In Changing, IoT-Driven Market](https://www.androidheadlines.com/2018/03/risc-v-stands-gain-changing-iot-driven-market.html) by Daniel Golightly, Android Headlines

[Fifty (or Sixty) Years of Processor Development…for This?](https://www.eejournal.com/article/fifty-or-sixty-years-of-processor-developmentfor-this/) By Steven Leibson, EE Journal

[‘Computing’s Nobel Prize” Winners Paved The Way To Smartphone Chips](https://www.wired.com/story/computings-nobel-prize-winners-paved-the-way-to-smartphone-chips/) by Klint Finley, WIRED

[Computer Chip Visionaries Win Turing Award](https://www.nytimes.com/2018/03/21/technology/computer-chips-turing-award.html) by Cade Metz, The New York Times

[Big tech signs up for new open source rival to ARM](https://fudzilla.com/news/processors/45946-big-tech-signs-up-for-new-open-source-rival-to-arm) by Nick Farrell, Fudzilla

[Interview with Rick O'Connor of RISC-V Foundation](http://www.eenewseurope.com/news/interview-rick-oconnor-risc-v-foundation) by Peter Clarke, eeNews Europe

We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!

Thanks for your continued support!  
Until next time,  
Jack Kang

_We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!_

We are thrilled to announce that we raised $50.6 million in our Series C funding round! Thanks to our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement!

Welcome to the first iteration of our bi-monthly newsletter, The SiFive Download! On a regular cadence, we will plan to give you a download on all things SiFive – from the events we will be attending to the articles we’ve been featured in. This newsletter is intended to give you a glimpse under the SiFive hood.

The first iteration of the SiFive Download marks a year to the day that we first publicly shared our company’s visions, products, and goals with the world. And while we anticipated success, we have been blown away – and continue to be – by the amount of support SiFive, RISC-V and the open-source movement has received.

On July 11, 2016, we introduced the industry’s first open-source chip platforms with our [Freedom U500 and Freedom U300](https://www.sifive.com/products/freedom/) family SoC platforms. The [FE310](https://www.sifive.com/products/freedom-e310/), the first chip available on our Freedom E platform, is housed on the [HiFive1](https://www.sifive.com/products/hifive1/) development board – which has been purchased and shipped more than 1,000 times to developers in over 40 countries. Later that winter, SiFive was named “Startup of the Year” at the UBM Annual Creativity in Electronics (ACE) Awards, capping a banner year for the company.   

Just this past May, we announced the availability of [Coreplex IP](https://www.youtube.com/watch?v=byE-E8QKTX4), the fastest way to license RISC-V cores and a radical transformation of the IP licensing process. Along with the launch, our website received a facelift – making it easier than ever to get your hands on custom IP through our streamlined study, evaluate, buy purchase process.

<table>
<tbody>
<tr>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/Step1.jpg?t=1499745556350" alt="Step 1: Study" /></td>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/Step2.jpg?t=1499745556350" alt="Step 2: Evaluate" /></td>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/Step3.jpg?t=1499745556350" alt="Step 3: Buy" /></td>
</tr>
</tbody>
</table>

#### Step 1: Study
Get immediate access to all the documentation and datasheets that you need. No registration, no NDA needed.

#### Step 2: Evaluate
Benchmark your code on real hardware. Register for immediate access to FPGA bitstreams, or sign up for a free evaluation of RTL.

#### Step 3: Buy
Changing the way people buy IP. DocuSign and download. We offer fair and transparent pricing, with a simple 7-page license.

### Upcoming Events
- [Hot Chips, August 20-22, 2017](https://www.hotchips.org/)
  - On day one of the conference, SiFive Co-founder and CTO Yunsup Lee will give a presentation on SiFive’s Freedom SoCs, the industry’s first open-source RISC-V chips. 
- [7th RISC-V Workshop, November 28-30, 2017](https://riscv.org/)
  - The call for papers for the 7th RISC-V Workshop is now [open](https://riscv.org/2017/06/7th-risc-v-workshop-call-for-papers/)! 

### Forum Highlights
There is a lot going on over at the [SiFive Forum](https://forums.sifive.com/), which you can access through the SiFive site. The forums are chalked full of valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that have our attention (and will now have yours, too!):

- [Freedom Studio Beta 2 – Now live!](https://forums.sifive.com/t/freedom-studio-beta-2/600)
- [Linux on the Arty board](https://forums.sifive.com/t/linux-on-the-arty-board/611)
- [The RISCY BUSINESS Question](https://forums.sifive.com/t/the-big-riscy-business-question-thread/531/8)

### [Featured Developer of the Month](https://forums.sifive.com/t/hifive1-cinque-case/577)
Our world centers around you - the developers, the engineers, the users, the dreamers. It’s all of your contributions to RISC-V and open-source that make what we do at SiFive possible.

This month’s featured developer is [Dave Grubb](https://twitter.com/DavidGrubb18), who recently shared his design for a 3D printed case to house the HiFive1 development board (Photos Below). Great stuff, David! 

We’d love to feature your SiFive project in the next newsletter - let us know what you are working on!

<table>
<tbody>
<tr>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/1.jpg?t=1499745556350" /></td>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/2.jpg?t=1499745556350" /></td>
<td><img src="https://cdn2.hubspot.net/hub/3020607/hubfs/3.jpg?t=1499745556350" /></td>
</tr>
</tbody>
</table>

### Blog Posts
If you know us, you know that we are a chatty group. Here’s what has been on our minds (and our blog) over the past few months:

[The FE310 is in a Museum – Which is Pretty Cool](https://www.sifive.com/blog/2017/06/14/the-fe310-is-in-a-museum-which-is-pretty-cool/) by Jack Kang

[SiFive; The Journey to Becoming the Easiest Company to do Business With](https://www.sifive.com/blog/2017/05/07/sifive-the-journey-to-becoming-the-easiest-company-to-do-business-with/) by Sander Arts

[Employee Q&A: Introducing Renxin Xia](https://www.sifive.com/blog/2017/03/15/employee-qa-introducing-renxin-xia/) by Staff

[RISC-C GCC is Upstreamed!](https://www.sifive.com/blog/2017/03/03/risc-v-gcc-is-upstreamed/) By Andrew Waterman

[Women in Open Source: You DO Belong Here](https://www.sifive.com/blog/2017/02/08/women-in-open-source-you-do-belong-here/) by Megan Wachs

### SiFive in the Press
From the release of the FE310 and HiFive1, to the news around funding, RISC-V adoption and the availability of Coreplex IP, SiFive has been featured in a variety of publications since we launched. Want to see who has been talking about SiFive for the past 12 months? Let’s take a look!

[Two Bay Area Startups Raise Venture Capital Around Programmable Chips](http://www.bizjournals.com/sanjose/news/2017/05/08/flex-logic-sifive-funding-programmable-chips.html) by Luke Stangel, Silicon Valley Business Journal

[SiFive Raises $8.5 Million For Licensable Custom Microprocessors](https://venturebeat.com/2017/05/08/sifive-raises-8-5-million-for-licensable-custom-microprocessors/) by Dean Takahashi, VentureBeat

[Open-source Chip Mimics Linux's Path to Take on Closed x86, ARM CPUs](http://www.itworld.com/article/3194356/internet-of-things/open-source-chip-mimics-linuxs-path-to-take-on-closed-x86-arm-cpus.html) by Agam Shah, IDG

[RISC-V Cores Get Support, Fees](http://www.eetimes.com/document.asp?doc_id=1331690) by Rick Merritt, EE Times

[SiFive: Low-Cost Custom Silicon](http://semiengineering.com/sifive-low-cost-custom-silicon/) by Ed Sperling, SemiEngineering

[Will RISC-V Rescue the Internet of Things?](http://electronicdesign.com/blog/will-risc-v-rescue-internet-things) By Bill Wong, Electronic Design

[SiFive Launches Open Source RISC-V Custom Chip](http://venturebeat.com/2016/11/29/sifive-launches-open-source-risc-v-custom-chip/) by Dean Takahashi, VentureBeat

[SiFive Execs Share Ideas on Their RISC-V Strategy](https://www.semiwiki.com/forum/content/6257-sifive-execs-share-ideas-their-risc-v-strategy.html) by Don Dingee, SemiWiki

[SiFive: a RISC-V Fabless Semiconductor Company](https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2016/09/07/sifive-a-risc-v-fabless-semiconductor-company) by Paul McLellan, Cadence

[SiFive Unveils Freedom Platforms for RISC-V-Based Semi-Custom Chips](http://www.anandtech.com/show/10488/sifive-unveils-freedom-platforms-for-riscvbased-semicustom-chips) by Anton Shilov, AnandTech

[This New Chip Startup Wants To Bring Open Source To A Stagnant Industry](http://www.forbes.com/sites/aarontilley/2016/07/11/risc-v-sifive-chips/) by Aaron Tilley, Forbes

[Backers of Open Source Chips Launch Startup](http://www.wsj.com/articles/backers-of-open-source-chips-launch-startup-1468242001) by Don Clark, Wall Street Journal

### RISC-V in the News

We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

[UltraSoC to Offer Processor Trace Support For RISC-V](https://www.electronicsweekly.com/news/business/502285-2017-06/) by David Manners, Electronics Weekly

[FPGA IDE Zeros in on RISC-V](http://www.electronicdesign.com/industrial-automation/fpga-ide-zeros-risc-v) by Bill Wong, Electronic Design

[RISC-V Shanghai](https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2017/05/24/risc-v-shanghai-2) by Paul McLellan, Cadence 

[Death of Moore’s Law Makes Open Hardware Possible](https://blog.hackster.io/death-of-moores-law-makes-open-hardware-possible-7aaad86e47bf) by Alsdair Allan, Hackster.io

_We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!_

The first iteration of the SiFive Download marks a year to the day that we first publicly shared our company’s visions, products, and goals with the world. We have been blown away by the amount of support SiFive, RISC-V and the open-source movement has received.

These last few months have been equal parts busy, exciting, and promising. We are eager to catch you up on the latest happenings at SiFive and within the RISC-V ecosystem as a whole.

We had a blast this week at the 7th RISC-V Workshop, which drew more than 500 attendees! In addition to seeing some [awesome swag](https://twitter.com/SiFiveInc/status/935539163033686017), we heard great news from presenting companies and partners, such as workshop host Western Digital, who announced its intention to shift the 1 billion cores it ships annually in its products to RISC-V. We were also excited to be named by several presenting companies, including Lauterbach and the University of Washington, as a leading partner in the emerging RISC-V ecosystem. At the evening poster session reception, our demo table had great traffic with plenty of visitors from potential customers and partners.

We also had the honor of partnering with some of the industry’s leading companies and announced the following at the workshop:

- **[An extended partnership with Microsemi](https://www.sifive.com/posts/2017/11/28/sifive-and-microsemi-expand-relationship-with-strategic-roadmap-alignment-and-linux-capable-risc-v-development-board/):** Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based Freedom Unleashed 500 (U500) platform and Microsemi’s PolarFire FPGAs.
- **[Membership in GLOBALFOUNDRIES’ FDXcelerator Partner Program](https://www.sifive.com/posts/2017/11/28/sifive-joins-fdxcelerator-program-to-bring-risc-v-core-ip-to-globalfoundries-22fdx-process-technology/):** SiFive has joined the GF program that brings together select partners to integrate their products or services into validated, plug-and-play design solutions. This provides GF customers access to SiFive RISC-V Core IP alongside a broad set of quality offerings specific to GF’s 22FDX technology

And as you likely guessed, we had a lot to talk about! Did you miss it? No worries, the video links to our presentations will soon be up on [riscv.org](https://riscv.org/).

### Introducing [DesignShare](https://www.sifive.com/designshare/), our revolutionary ecosystem created to spur innovation
Earlier this summer, we launched a movement to further accelerate our mission to democratize access to custom silicon: DesignShare. DesignShare is a new concept in which partnering companies make IP and components available to emerging markets and companies at a reduced upfront cost to help spur innovation in the industry.

Similar to how the foundry model created an entirely new class of fabless semiconductor company (which no longer had to build and support its own foundry), DesignShare reduces the barriers that traditionally block all but the largest industry players from access to custom silicon and world class IP and creates an entirely new group of companies that can innovate at the hardware and software level.

In just a few short months, the DesignShare initiative has granted system designers access to a wide range of technology. Companies including Rambus, Flex Logix, UltraSoC, Analog Bits and eMemory have all enlisted to make it easier and more flexible for designers to employ SiFive-based RISC-V cores in future designs. In addition to PLLs and SERDES IP, system designers can include cryptographic cores, embedded analytics, debug and trace technology, embedded, reconfigurable FPGA and logic-based, non-volatile memory to their SoCs.

Are you interested in being a part of the evolution? [Let’s talk](https://www.sifive.com/about/contact/)!

**Ready for our next webinar?**  
**Date:** Jan.17, 2018, at 10:30 a.m. PST. 

Part three of our “Introduction to SiFive RISC-V Core IP” webinar will demonstrate how to use the evaluation versions of our E31 and E51 RISC-V Core IP. In this webinar, we will download and program an Arty FPGA board with one of the evaluation images, and use Freedom Studio to program load and debug a program.

<button disabled>Register Now!</button>

Missed our last webinar? No worries! You can find both session recordings [here](https://info.sifive.com/risc-v-webinar) and download the materials presented.

### Forum Highlight
The [SiFive Forums](https://forums.sifive.com/) are buzzing this month! It’s packed with valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that caught our attention (and will now have yours, too!):

- [Reading Memory](https://forums.sifive.com/t/reading-memory/701)
- [E310 Package Dimensions](https://forums.sifive.com/t/e310-package-dimensions/587/5)
- [Maximum serial clock frequency on HiFive1?](https://forums.sifive.com/t/maximum-serial-clock-frequency-on-hifive1/878)

### Featured Project Of the Month
<div><img alt="rv-badge" src="https://cdn2.hubspot.net/hub/3020607/hubfs/rv-badge.jpg?t=1512056018368" /></div>

Our view of the world centers around the developer, the engineer, the user, the dreamer. It’s you who are contributing to RISC-V and open-source, which makes what we do at SiFive possible.

This month’s featured project comes from Antmicro, which contributed the design of a [RISC-V electronic badge](http://badge.antmicro.com/) for the 7th RISC-V Workshop. Speakers and journalists were sporting these limited edition badges developed in collaboration with SiFive and co-sponsored by the Foundation. Programmable from their smartphones, badge-wearers (can we call them badgers??) were able to display their name and whatever message of their choice from the e-ink screen. Best of all, the badge is completely open sourced and all the design files and software are available. It’s consisted of a carrier card with a reusable, socket-based small RISC-V SoC module that can be removed and used for prototyping other interesting RISC-V projects.  

We’d love to feature your SiFive project in the next newsletter - let us know what you are working on!

### More Blog Posts
What’s been on our minds, you ask? Quite a few things, but here are some of our top blogs over the past month:

[Awards Season Brings Big Surprises](https://www.sifive.com/blog/2017/11/16/award-season-brings-big-surprises/) by Jack Kang

[Analog Bits Clocks into the DesignShare Ecosystem](https://www.sifive.com/blog/2017/11/15/analog-bits-clocks-into-the-designshare-economy/) by Jack Kang

[The DesignShare Ecosystem Expands Its Catalog of IP to include eMemory’s Logic NVM](https://www.sifive.com/blog/2017/11/09/the-designshare-ecosystem-expands-its-catalog-of-ip-to-include-ememorys-logic-nvm/) by Jack Kang

[All Aboard, Part 7: Entering and Exiting the Linux Kernel on RISC-V](https://www.sifive.com/blog/2017/10/23/all-aboard-part-7-entering-and-exiting-the-linux-kernel-on-risc-v/) by Palmer Dabbelt

[A Core By Any Other Name…](https://www.sifive.com/blog/2017/10/11/a-core-by-any-other-name/) by Jack Kang

### SiFive in the Press
Want to see who has been talking about SiFive recently? Let’s take a look!

[SiFive Building RISC-V Ecosystem, One Partnership at a Time](https://www.allaboutcircuits.com/news/sifive-building-risc-v-ecosystem-one-partnership-at-a-time/) by Majeed Ahmad, AllAboutCircuits.com 

[SiFive Adds Flex Logix eFPGA IPs to DesignShare Initiative](https://www.allaboutcircuits.com/news/sifive-adds-flex-logix-efpga-ips-to-designshare-initiative/) by Chantelle Dubois, AllAboutCircuits.com

[DesignShare is all About Enabling Design Wins!](https://www.semiwiki.com/forum/content/7126-designshare-all-about-enabling-design-wins.html) by Daniel Nenni, SemiWiki

[FlexLogix joins SiFive’s DesignShare program](https://www.semiaccurate.com/2017/11/02/flexlogix-joins-sifives-designshare-program/) by Charlie Demerjian, SemiAccurate

[Flex Logix makes eFPGA available for SiFive design environment](https://www.electronicsweekly.com/news/business/flex-logix-makes-efpga-available-sifive-design-environment-2017-11/) by David Manners, ElectronicsWeekly.com

[The Week In Review: Design](https://semiengineering.com/the-week-in-review-design-103/) by Jesse Allen, SemiEngineering

### RISC-V in the News
We’re always keeping an eye on RISC-V; after all, our founders invented it! Speaking of, did you hear the RISC-V ecosystem surpassed 100 members globally? We’re excited to see the growth! Check out the news here, and more of the latest conversations around the RISC-V ISA:

[UltraSoC selected by Microsemi for growing RISC-V product rangen Source Software Based Big Data Analytics Technology to Increase Speed by Up to 100 Times](https://www.eejournal.com/industry_news/hitachi-develops-opeultrasoc-selected-by-microsemi-for-growing-risc-v-product-rangen-source-software-based-big-data-analytics-technology-to-increase-speed-by-up-to-100-times/) by Staff, EE Journal

[Andes partners with EDA tool vendors for more RISC-V SoC support](http://www.eenewseurope.com/news/andes-partners-eda-tool-vendors-more-risc-v-soc-support), by Julien Happich, EE News Europe

[Microsemi Opens RISC-V Ecosystem with Industry Leaders](https://www.photonics.com/a62718/Microsemi_Opens_RISC-V_Ecosystem_with_Industry) by Staff, Photonics.com

Thanks so much for all of your continued support!  
Till next time,  
Jack Kang

_We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!_

These last few months have been equal parts busy, exciting, and promising. We are eager to catch you up on the latest happenings at SiFive and within the RISC-V ecosystem as a whole.

A new season, new partnerships and a new frontier.

Earlier this month, we took a huge step in democratizing access to custom silicon when we unveiled our newest core, the [U54-MC Coreplex](https://www.sifive.com/products/coreplex-risc-v-ip/u54-mc/) - the industry’s first RISC-V based, 64-bit, quadcore application processor with support for full featured operating systems including Linux, Unix and FreeBSD.

The standard U54-MC Coreplex contains four U54 CPUs along with a single E51 CPU, and is the first Coreplex to include multicore support and cache coherence. Each U54 CPU utilizes a highly efficient five-stage in-order pipeline. The U54 cores support the RV64GC ISA, which is expected to be the standard for Linux-based RISC-V devices. The 64-bit E51 CPU serves as a management core and is fully coherent with the main U54 cores. The U54-MC Coreplex is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways, and smart IoT devices.

Since we [launched the industry’s first open-source RISC-V SoC](https://www.sifive.com/posts/2016/07/11/sifive-introduces-industrys-first-open-source-chip-platforms/) back in July 2016, we’ve had the pleasure of pushing the boundaries of the RISC-V ecosystem and have been delighted by the support that SiFive – and RISC-V – has gained from the greater tech community. We are so excited to continue to support the RISC-V ecosystem and the U-54 MC Coreplex will allow us to provide more support than ever before.

### The First RISC-V Webinar Was Great - Let’s do Another!
On Sept. 12, we held part one of our first-ever webinar series “[An Introduction to RISC-V for Embedded Developers](https://info.sifive.com/risc-v-webinar),” where we laid the groundwork and explained the basics of the RISC-V instruction set. Thank you to everyone who joined - we hope you all enjoyed it as much as we did!

On Oct. 17, we will host part two of the three-part RISC-V webinar series titled, “Introduction to SiFive IP,” which will explore the SiFive Coreplex IP products, E31 Coreplex and E51 Coreplex.

Weren’t able to join part I? Attended part I and looking to dive even deeper into the RISC-V ISA?

<button disabled>Register Now!</button>

### Eat, Drink, Connect - More to come from SiFive HQ
<div><img alt="eat drink" src="https://cdn2.hubspot.net/hub/3020607/hubfs/eatdrink.jpg?t=1507649996974" /></div>

In coordination with the Linaro Connect conference held in San Francisco earlier this month, we had the pleasure of hosting a group of open-source developers at our new office in San Mateo! Those who made the trip were met with food and beverages, a short presentation from Yunsup and signed RISC-V books by the inventors themselves.

We would like to say a quick thank you to everyone that made it out! Looking forward to hosting more events in the very near future!

### All Aboard: A Weekly Update on RISC-V 
<div><img alt="All Aboard logo" src="https://cdn2.hubspot.net/hub/3020607/hubfs/All%20Aboard%20logo%20(1).jpg?t=1507649996974" /></div>

In the last SiFive Download, we introduced Palmer Dabbelt’s blog series, “All Aboard,” a weekly update on the RISC-V ecosystem. Check out what Palmer has been up to since the last newsletter:

- [All Aboard, Part 5: Per-march and per-mabi Library Paths on RISC-V systems](https://www.sifive.com/blog/2017/09/18/all-aboard-part-5-risc-v-multilib/)
- [All Aboard, Part 4: The RISC-V code models](https://www.sifive.com/blog/2017/09/11/all-aboard-part-4-risc-v-code-models/)
- [All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain](https://www.sifive.com/blog/2017/08/28/all-aboard-part-3-linker-relaxation-in-riscv-toolchain/)

### Upcoming Events
Did you miss us at the Linley Conference earlier this month? No sweat! Check out our slides from Jack’s presentation [here](http://static.dev.sifive.com/slides/SiFive-U54-MC.pdf).

- [International System-on-Chip Conference](http://www.socconference.com/), October 18-19, 2017
  - The Linley Processor Conference isn’t the only event Jack is speaking at in October. Make sure you catch him at the International SoC Conference held at UC Irvine!  
- [7th RISC-V Workshop](https://riscv.org/), November 28-30, 2017
  - The 7th RISC-V Workshop hosted by Western Digital in Milpitas, CA is just two months away! This is a must attend event for any and all who are interested in the RISC-V ISA - register here.
- [ESC Silicon Valley](http://escsiliconvalley.com/), December 5-7, 2017
  - At our second go around at ESC Silicon Valley, we will be taking a look at the growing RISC-V ecosystem, performance of open source-based embedded cores and solutions to the development challenges in using open source-based hardware for commercial projects. In addition, our very own Megan Wachs will be joining a “women in tech” panel!

### Forum Highlight
There is lots going on over at the [SiFive Forums](https://forums.sifive.com/), which you can access through the SiFive site. The forums are chalked full of valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that have our attention (and will now have yours, too!):

- [LoFive RISC-V](https://forums.sifive.com/t/lofive-risc-v/744)
- [Is it possible to brick the HiFive board?](https://forums.sifive.com/t/is-it-possible-to-brick-the-hifive-board/751)
- [SVD file for E310-G000](https://forums.sifive.com/t/svd-file-for-e310-g000/731)

### Featured Developer Of the Month
Our view of the world centers around the developer, the engineer, the user, the dreamer. It’s you who are contributing to RISC-V and open-source, making what we would do at SiFive possible.

One of the coolest things about what we do is seeing all the various implementations and iterations of RISC-V based projects. And (not to play favorites), but perhaps one of the coolest implementations we’ve seen came by the way of QWERTY Embedded Design’s [Michael Welling](https://twitter.com/qwertyembedded) and the LoFive board. The LoFive board has generated tremendous buzz in Twittersphere - and for good reason! This thing seriously rocks; [check it out](https://hackaday.io/project/26909-lofive)!

<div><img alt="lofive" src="https://cdn2.hubspot.net/hub/3020607/hubfs/lofive.jpg?t=1507649996974" /></div>

We’d love to feature your SiFive project in the next newsletter - [let us know](mailto:info@sifive.com) what you are working on!

### More Blog Posts
If you know us, you know that we are a chatty group. Here’s what has been on our minds (and our blog) over the past few months:

[Introducing the U54-MC Coreplex IP - The First RISC-V Core with Linux Support](https://www.sifive.com/blog/2017/10/06/introducing-u54-mc-coreplex-ip-the-first-risc-v-core-with-linux-support/) by Jack Kang  

[RISC-V 101 Webinar](https://info.sifive.com/risc-v-webinar) by Jack Kang

[SiFive; The Journey to Becoming the Easiest Company to do Business With](https://www.sifive.com/blog/2017/05/07/sifive-the-journey-to-becoming-the-easiest-company-to-do-business-with/) by Sander Arts

[Employee Q&A: Introducing Renxin Xia](https://www.sifive.com/blog/2017/03/15/employee-qa-introducing-renxin-xia/) by Staff

### SiFive in the Press
Want to see who has been talking about SiFive recently? Let’s take a look!

[2018 Will be The Year of The RISC-V Linux Processors](http://www.fudzilla.com/news/processors/44667-2018-will-be-the-year-of-the-risc-v-linux-processors) by Nick Farrell, Fudzilla

[Linux Now Has its First Open Source RISC-V Processor](https://www.designnews.com/content/linux-now-has-its-first-open-source-risc-v-processor/71646867257598) by Chris Wiltz, Design News

[SiFive Announces RISC-V SoC](https://hackaday.com/2017/10/04/sifive-announces-risc-v-soc/) by Brian Benchoff, Hackaday

[Hands-On HiFive RISC-V](http://www.electronicdesign.com/industrial-automation/hands-hifive-risc-v) by Bill Wong, Electronic Design

[Naveed Sherwani Takes Reins at SiFive](https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2017/09/05/naveed-sherw) by Paul McLellan, Cadence

[SiFive’s Chief Executive on Opening a Chip Design Factory](http://www.electronicdesign.com/embedded-revolution/sifive-s-chief-executive-opening-chip-design-factory) by James Morra, Electronic Design

### RISC-V in the News
We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

[RISC-V Paper by Imperas at 15th International System-on-Chip (SoC) Conference 2017](https://www.eejournal.com/industry_news/risc-v-paper-by-imperas-at-15th-international-system-on-chip-soc-conference-2017/) by Staff, EE Journal

[The Natural Evolution of Artificial Intelligence](http://www.barrons.com/articles/the-natural-evolution-of-artificial-intelligence-1506142127) by Tiernan Ray, Barron’s

[UltraSoC Expands After $6m Investment](http://www.newelectronics.co.uk/electronics-news/ultrasoc-expands-after-6m-investment/160705/) by Graham Pitcher, New Electronics

[Roundtable: Experts Discuss Key Design Engineer Challenges](https://www.ecnmag.com/article/2017/09/roundtable-experts-discuss-key-design-engineer-challenges) by Staff, ECN Magazine

_We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!_

Our newest core, the U54-MC Coreplex is the industry’s first RISC-V based, 64-bit, quadcore application processor with support for full featured operating systems including Linux, Unix and FreeBSD.

Welcome the newest member of the SiFive family, U54-MC Coreplex!

_On August 15, we announced that regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry._

![Naveed headshot](https://cdn2.hubspot.net/hub/3020607/hubfs/Naveed%20headshot.jpg?t=1503943861496)

Hello, SiFive Download readers! It’s great to e-meet you all. I am so honored and excited by the opportunity to join SiFive at such a pivotal time in the evolution of RISC-V. Over the past year, SiFive has achieved some significant milestones: we launched our Freedom SoC platforms, released our Coreplex IP, introduced a brand new IP licensing process and most recently, capped off a recent funding round that will make it possible for our organization to continue to drive innovation for the RISC-V community. But believe me when I tell you - we are just getting started.

When people ask me what attracted me to join SiFive, I tell them two things: Over the course of my 30-plus year career, I’ve been involved in the development of more than 300 chips. And never have I seen the potential for such a radical sea change in the industry. Second, there is no doubt in my mind that RISC-V will succeed - and no one is better positioned to take advantage of its success than SiFive.

The semiconductor industry needs to fundamentally change if it is to survive. We need to attract the best minds in technology to solve these thorny hardware challenges, and we need to enable innovation in every corner of the globe, not just four or five design centers. I’m excited to be on this journey together, and would love to hear from you. My inbox is always open - please drop me a line at [nsherwani@sifive.com](mailto:nsherwani@sifive.com), or introduce yourself at one of the many industry conferences SiFive will attend in the coming months.

-- Naveed

### The (New) News Doesn’t Stop There! Introducing a RISC-V Webinar Series
This may not be as cool as a new chief executive - but it’s pretty darn close! On September 12, we will hold part one of a three-part (and our first ever) webinar series titled, “Getting Started with SiFive Coreplex IP”.

For part one - An Introduction to RISC-V for Embedded Developers - we will lay the groundwork and explain the basics of the RISC-V instruction set. This webinar is intended to give embedded developers a brief introduction into the RISC-V architecture. It assumes no prior RISC-V experience, so beginners welcome!

Want to learn more about the RISC-V ISA? Want a refresh on things you already know? 

<button disabled>Register Now!</button>

### All Aboard: A Weekly Update on RISC-V 
<div><img alt="All Aboard logo" src="https://cdn2.hubspot.net/hub/3020607/hubfs/All%20Aboard%20logo%20(1).jpg?t=1503943861496" /></div>

That’s right - more new SiFive happenings to recap. Earlier this month, SiFive engineer Palmer Dabbelt launched a blog series called “All Aboard”, a weekly update on the RISC-V ecosystem. Check out the posts that have gone live thus far:

- [All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain](https://www.sifive.com/blog/2017/08/28/all-aboard-part-3-linker-relaxation-in-riscv-toolchain/)
- [All Aboard, Part 2: Relocations in ELF Toolchains](https://www.sifive.com/blog/2017/08/21/all-aboard-part-2-relocations/)
- [All Aboard, Part 1: The -march, -mabi, and -mtune arguments to RISC-V Compilers](https://www.sifive.com/blog/2017/08/14/all-aboard-part-1-compiler-args/)
- [All Aboard, Part 0: Introduction](https://www.sifive.com/blog/2017/08/07/all-aboard-part-0-introduction/)
 

### Upcoming Events
<div><img alt="Yunsup Eclipse" src="https://cdn2.hubspot.net/hub/3020607/hubfs/Yunsup_Eclipse.jpg?t=1503943861496" /></div>

Were you unable to catch us at Hot Chips earlier this month? Didn’t get a chance to see Yunsup look at totality? No sweat! As Naveed mentioned, we will be all over the map at various industry conferences as 2017 winds to a close. 

- [TSMC 2017 Open Innovation Forum](http://www.hwacomms.com/TSMC2017/OIP/vna/Attendee/index.html), September 13, 2017
  - Drop by and say hello to us at booth 215, where we will be showing off our latest innovations and talking all things SiFive, RISC-V and open-source!
- [Linley Processor Conference](http://www.linleygroup.com/events/event.php?num=43), October 4-5, 2017
  - You will not want to miss this - Jack is set to debut the our newest Coreplex IP design, the U54 Coreplex. [Register now](http://www.linleygroup.com/events/register.php?num=43)!
- [International System-on-Chip Conference](http://www.socconference.com/), October 18-19, 2017
  - The Linley Processor Conference isn’t the only event Jack will be speaking at in October. Make sure you catch him at the International SoC Conference held at UC Irvine!  
- [7th RISC-V Workshop](https://riscv.org/), November 28-30, 2017
  - The [call for papers](https://www.softconf.com/h/riscv7thwkshp/) for the 7th RISC-V Workshop hosted by Western Digital in Milpitas, CA is live! Make sure to get your submissions in by the Sept. 17 deadline - hope to see you all there!
- [ESC Silicon Valley](http://escsiliconvalley.com/), December 5-7, 2017
  - At our second go around at ESC Silicon Valley, we will be taking a look at the growing RISC-V ecosystem, performance of open source-based embedded cores and solutions to the development challenges in using open source-based hardware for commercial projects.

### Forum Highlight
There is lots going on over at the [SiFive Forums](https://forums.sifive.com/), which you can access through the SiFive site. The forums are chalked full of valuable content that can answer your questions and curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that have our attention (and will now have yours, too!):

- [RISC-V External Debug](https://forums.sifive.com/t/risc-v-external-debug/690)
- [Freedom E300 Port to Zedboad](https://forums.sifive.com/t/freedom-e300-port-to-zedboard/694)
- [Freedom Studio on Linux](https://forums.sifive.com/t/freedom-studio-on-linux/685)

### Featured Developer Of the Month
Our view of the world centers around the developer, the engineer, the user, the dreamer. It’s you who are contributing to RISC-V and open-source, making what we would do at SiFive possible.

This month’s feature developer is Mio Iwakura, better known as “[Moitatsu](https://twitter.com/miotatsu)” to his fans and followers. In addition to being an active member on the [SiFive Forums](https://forums.sifive.com/users/miotatsu/activity), Mio has his own RISC-V YouTube series called “[RISCY BUSINESS](http://riscy.tv/)”, in which he has developed a handmade toolchain for RISC-V. Mio had Yunsup and Andrew on the series back in May - [check it out](https://www.youtube.com/watch?v=Df-o29DkqWw)!

We’d love to feature your SiFive project in the next newsletter - [let us know](mailto:info@sifive.com) what you are working on!

### More Blog Posts
If you know us, you know that we are a chatty group. Here’s what has been on our minds (and our blog) over the past few months:

[Our New Partnership with Rambus and the DesignShare Economy](https://www.sifive.com/blog/2017/08/24/partnership-with-rambus-and-designshare-economy/) by Jack Kang

[The FE310 is in a Museum – Which is Pretty Cool](https://www.sifive.com/blog/2017/06/14/the-fe310-is-in-a-museum-which-is-pretty-cool/) by Jack Kang

[SiFive; The Journey to Becoming the Easiest Company to do Business With](https://www.sifive.com/blog/2017/05/07/sifive-the-journey-to-becoming-the-easiest-company-to-do-business-with/) by Sander Arts

[Employee Q&A: Introducing Renxin Xia](https://www.sifive.com/blog/2017/03/15/employee-qa-introducing-renxin-xia/) by Staff

### SiFive in the Press
Want to see who has been talking about SiFive recently? Let’s take a look!

[SiFive Appoints Naveed Sherwani as CEO](http://www.eenewseurope.com/news/sifive-appoints-naveed-sherwani-ceo) by Peter Clarke, eeNews Europe

[Rambus Adds Security to RISC-V](http://www.eetimes.com/document.asp?doc_id=1332175) by Rick Merritt, EE Times

[SiFive RISC-V and the Future of Computing!](https://www.semiwiki.com/forum/content/6964-sifive-risc-v-future-computing.html) By Daniel Nenni, SemiWiki

[Custom Processor Maker SiFive Appoints Intel Veteran as CEO](https://venturebeat.com/2017/08/15/custom-processor-maker-sifive-appoints-intel-veteran-as-ceo/) by Dean Takahashi, VentureBeat

### RISC-V in the News
We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

[Nvidia CEO Huang: Big Data, Self-Driven Cars, Gaming the ‘Big Vectors’](http://www.barrons.com/articles/nvidia-ceo-huang-big-data-self-driven-cars-gaming-the-big-vectors-1502407194) by Tiernan Ray, Barron’s
_Look who Huang called an open-source company!_

[IP Challenges Ahead](https://semiengineering.com/ip-challenges-ahead/) by Brian Bailey, SemiEngineering

[Does RISC-V Mean Open Source Processors](https://www.codasip.com/2017/08/08/does-risc-v-mean-open-source-processors/) by Roddy Urquhart, Codasip

[VexRiscv: A Modular RISC-V Implementation for FPGA](http://hackaday.com/2017/07/21/vexriscv-a-modular-risc-v-implementation-for-fpga/) by Al Williams, Hackaday

_We would love to hear from you - reply to this email with any questions or inquiries and we will get right back to you!_

Regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry.

Krste Asanovic on the Past, Present and Future of RISC-V and SiFive

ASPLOS Keynote: The Golden Age of Compiler Design in an Era of HW/SW Co-design

SiFive RISC-V Software Ecosystem, Featuring IAR Systems, Lauterbach, SEGGER, and more

The Heart of RISC-V Software Development is Unmatched

Hong-Rong Hsu has been leading and actively contributing to the Open Source Software team since 2019 and is currently serving as a Team Manager at SiFive.

In this role, he is responsible for both overseeing and hands-on development of AI/ML software, as well as managing AI/ML model e2e deployment.

Prior to joining SiFive, Hong-Rong gained valuable experience at MediaTek (2010–2018) and Bitmain (2018–2019).

His expertise spans AI/ML, system software, compilers, and RISC-V, with a strong focus on driving innovation and contributing to technical advancements in these areas.

Sign up to Watch this Webinar

Discover how RISC-V drives cutting-edge AI/ML technology.

Join us for an engaging webinar as we explore how SiFive is revolutionizing AI/ML deployment on RISC-V platforms. In this session, we'll dive into the SiFive AI/ML Software Stack, specifically designed for RISC-V, and demonstrate how to seamlessly deploy Pytorch Llama models to SiFive Intelligence platforms.

Discover the challenges of optimizing large language models (LLMs) and learn about our approach to achieving real-time Llama performance using the MLIR-based IREE compiler and runtime. This webinar is a must-attend for those interested in cutting-edge AI/ML solutions on RISC-V architectures.

Sign up to Download

Advanced LLM Optimization and Deployment on RISC-V - Chinese.pdf

Discover how RISC-V drives cutting-edge AI/ML technology

LLM Optimization and Deployment on SiFive Intelligence

The SiFive Connect webinar series is designed to be highly educational   and interactive, offering attendees a direct connection to industry   experts. Each one-hour long webinar will take place twice on the same   day – once at 9 a.m. PDT and again at 6 p.m. PDT enabling our global   audience to choose the time that works best for them.

Sam  Grove is the Director of Product Management for software at SiFive. He  has 15 years of experience in embedded software, operating systems and  community-driven open source software development. Prior to joining  SiFive, he worked at Arm for over six years in various software  architecture, applications and engineering management positions. Sam  earned his BS degree in electrical and electronics engineering at  California State University – Long Beach.

With  nearly three decades of experience in engineering, Bunnaroath Sou  serves as Engineering Manager of RISC-V Tools at SiFive. Prior to  joining SiFive, he was a principal engineer at Juniper Networks for over  eight years. Before that he was a technical leader at Cisco for almost  10 years. Bunnaroath earned his BE degree in computer engineering at the  University of Newcastle.

rapid-embedded-prototyping-with-sifive-software-presentation.pdf

Join us for a one-hour webinar to learn how to develop embedded software for RISC-V processors using the SiFive Freedom E SDK. We will review the environment dependencies, architecture, and implementation of the software and the processor-agnostic APIs. Based on an understanding of this, we will set up a development environment, compile, debug and run some benchmarks on a RISC-V processor. 

Rapid Embedded Prototyping with SiFive Software

Krste Asanovic, SiFive Co-Founder and Chief Architect took to the stage with Cliff Young , Google TPU architect And MLPerf Co-Founder to reveal how the latest SiFive Intelligence X280 processor with the new SiFive Vector Coprocessor Interface Extension (VCIX) is being used as the AI compute host to provide flexible programming combined with the Google MXU accelerator in the datacenter.

Krste Asanovic with Google's Cliff Young on The Future of AI at the AI Hardware

The SiFive 21G1 release offers new advanced computation capability with bit manipulation packages, half precision floating point, as well as code size reduction by up to 25%. SoC integration in terms of hardware and software has been optimized for more efficient computation, smaller size and faster time to market.


By using SiFive’s latest release of Core IP, defining and adopting a high-performance, high-efficiency, secure RISC-V processor for your next application or real-time SoC has never been more attractive. Save time and effort with SiFive’s unique support for Arm CoreSight to minimize workflow disruption, and broad tool ecosystem support for SiFive Insight Advanced Trace and Debug.


Learn more at our blog post here: SiFive Core IP 21G1

Graham has worked in the Semiconductor industry for over 25 years in various engineering and Processor IP Marketing roles. At SiFive, Graham is part of the Processor IP Product team, involved in whatever makes our customers successful with their SoC's using SiFive RISC-V processors.

210413 SiFive 21G1 Release Webinar-final.mp4

Join us in this webinar to learn about all of the enhancements to the SiFive™ RISC-V IP portfolio introduced in the 21G1 release. Product manager Graham Wilson will dive deep into the product updates, ranging from the ultra-capable SiFive U Series to the extremely popular SiFive E Series, offering up to 35% more performance for bit processing algorithms; and up to 25% smaller code size.

Enhancements to SiFive’s RISC-V IP Portfolio in the 21G1 Release

Krste is SiFive’s Chief Architect and a Co-Founder. is Professor Emeritus and a Professor of the Graduate School in the EECS Department at the University of California, Berkeley. He is currently Co-Director of the new Berkeley SLICElab, which is improving specialized computing ecosystems, and is also an Associate Director at the Berkeley Wireless Research Center.  He leads the RISC-V open ISA project at Berkeley (since 2010) and co-founded the RISC-V Foundation, which became RISC-V International. He is an ACM Fellow and an IEEE Fellow. Krste received his PhD from UC Berkeley, and a BA in Electrical and Information Sciences from the University of Cambridge.

Krste Asanovic, SiFive co-Founder, Chief Architect and RISC-V innovator, sat down to talk about how SiFive is solving real-world AI challenges and some of the applications where RISC-V is gaining rapid momentum. He also discussed how our latest innovations in high performance RISC-V computing are bringing exciting open standard solutions to AI and ML workloads.

You can watch the webinar here. We’ve also made his slides available for download here. 

SiFive-20240314-AI-Webinar-Presented.pptx.pdf

creating-agile-ai-systems-open-risc-v-solutions.mp4

Creating Agile AI Systems with Open RISC-V Solutions

As the Senior Vice President of Customer Experience at SiFive, Jack oversees the Customer Experience Group. He is responsible for all technical pre-sale activities as well as post-sale support and all customer program management. Prior to SiFive, Jack held a variety of senior business development, product management, and product marketing positions at both NVIDIA and Marvell. Jack earned his BS degree in electrical engineering and computer science from UC Berkeley. 

Jahoor Vohra is the Director of Field Application Engineering at SiFive. He has over 25 years of experience in senior-level engineering management. Prior to joining SiFive, he worked at Arm for over 18 years as FAE manager and then director of FAE. Jahoor earned his M.Sc. degree in VLSI circuit design at the University of Westminister, and his BE degree in electrical and electronics engineering at BVM Engineering College.

Embedding Intelligence Everywhere_with_7_series.pdf

embedded-intelligence-sifive-7-series-qna.pdf

As we move from the Internet of Things to the “Intelligence of Things,” compute platforms need to scale and be power efficient in order to cater to the entire spectrum of applications. In this one-hour webinar, we will see how the SiFive 7 Series Cores can enable several vertical markets and how its architecture scales across different needs.

Embedding Intelligence Everywhere with SiFive 7 Series Core IP

Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer-facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great.

210712 SiFive Performance Webinar-On-Demand-sm.mp4

The recently announced SiFive Performance family of processors is a significant milestone in SiFive’s commitment to delivering a complete, scalable portfolio of RISC-V cores.  In this webinar, Drew Barbier, Senior Director of Product Marketing, will introduce the Performance P270 and P550, both available now, and how SiFive continues to set the standard in RISC-V architecture.

Introducing the SiFive Performance Family of Products

SiFive Performance Family of Products Webinar

SiFive was founded by the creators of the free and open RISC-V architecture as a reaction to the end of conventional transistor scaling and escalating chip design costs.

Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great. 

SiFive 2 Series RISC-V Core IP - Webinar May 15.pdf

This webinar will introduce SiFive’s 2 Series Core IP, SiFive’s most-licensed Core Series. This webinar will cover the 2 Series Core architecture, the configurability of the 2 Series, and the Core Local Interrupt Controller (CLIC).

An Introduction to the RISC-V Architecture.pdf

This webinar will introduce RISC-V Architecture. It will provide an overview of RISC-V Modes, Instructions and Extensions, Control and Status Registers, and Interrupts. It is targeted at embedded developers who are new to RISC-V

Part I: An Introduction to the RISC-V Architecture

Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great.

Jack has held a variety of senior business development, management, and product marketing roles at both NVIDIA and Marvell, with a track record of successful, large scale design wins. Jack started his career as a frontend design engineer, focusing on CPU architecture and design. Jack received his BS degree in Electrical Eng. and Computer Science from UC Berkeley.

This webinar focuses on embedded developers who are interested in learning more about the RISC-V architecture. Part two introduces the SiFive RISC-V Core IP Products; the E31 RISC-V Core IP and the E51 RISC-V Core IP.

Part II: Introduction to SiFive RISC-V Core IP

Amy has designed and shipped hardware, software, and e-commerce solutions at innovative companies such as Bell Labs, Apple, General Magic, and Docker. At SiFive, she is responsible for the Core Designer and Chip Designer products.

From-a-Custom-2- Series-Core-to Hello-World-in-30 Minutes.pdf

A walk through configuring a custom E2 core using SiFive Core Designer, and then using Freedom Studio to write software targeting the custom core in the included RTL testbench and on an FPGA.

Part III: From a Custom 2 Series Core to 'Hello World'

Part III: From a Custom 2 Series Core to 'Hello World' in 30 Minutes

As the world moves toward the next industrial revolution, the need for artificial intelligence (AI) has become a quintessential requirement. Currently, data in the form of images is used as input to process the result/output, thereby enabling the human as well as the machine to make smart and intelligent decisions based on these processed outputs. For such intelligent decision making, we need a chip that can process real time data and provide us ~100% accurate results.

Join us in this webinar to learn more about our offerings for vision solutions. We will review the market needs, engineering and methodology for designing a RISC-V based SoC/ASIC for AI vision solutions. 

AI – Market requirement and future needs 

Engineering & Methodology – RISC-V based ASIC

David Lee, Director, Product Management at SiFive

SifiveVisionSolution.mp4

webinar-available-shortly.jpg

Join us in this webinar to learn about all of the enhancements to the SiFive™ RISC-V IP portfolio introduced in the 20G1 release, which is now available. Product manager Drew Barbier will dive deep into the product updates, including significant performance, power and area improvements, as well as new features like enhanced deterministic real-time capabilities, support for Xilinx UltraScale+-based VCU118 FPGA evaluation kit, support for FreeRTOS v.10, and the availability of fully integrated SiFive Shield™ Security and SiFive Insight™ Trace & Debug solutions. Numerous other enhancements will also be covered in this tutorial.

For a quick overview of the enhancements introduced in the 20G1 release, you can refer to our news release, and for a little more detail, you can read Drew’s blog. 

Drew Barbier,
Director, SiFive Core IP Product Management

20G1 - Connect-final.mp4

Enhancements to SiFive’s RISC-V IP Portfolio in the 20G1 Release

Currently, there is a huge demand in the market for storage systems. Reliability, high endurance and robustness are the essential features, which are very much required for such systems. Therefore, SSD controller-based storage solutions are most preferred for data centers.

Join us in this webinar to learn about how SiFive and our partners are driving innovations in silicon architectures for data center and enterprise systems. We will cover the storage market and technology trends, the importance of RISC-V and custom silicon in these applications, and case studies including an NVMe based RISC-V computational storage platform. 

How NVMe, computational storage and disaggregation of storage are disrupting traditional silicon architectures 

Application of SiFive RISC-V cores in next-generation SSD controllers and computational storage

Case studies: How our customers and eco-system partners are deploying SiFive RISC-V and custom silicon platforms to accelerate innovation in storage

Sudhir Mallya, Head of Datacenter Vertical  Marketing, SiFive, Inc. 

Ravi Thummarukudy, CEO of Mobiveil, Inc. 

sifive_storage_solution.mp4

How RISC-V and custom silicon platforms enable smart storage architectures

SiFive Storage Solutions: How RISC-V and custom silicon platforms enable smart storage architectures

Drew has worked in the semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great. 

In addition to serving as Chief Architect at SiFive, Krste is a Professor in the EECS Dept. at the UC, of California, Berkeley, where he also serves as Director of the ASPIRE Lab. Krste leads the RISC-V ISA project at Berkeley, and is Chairman of the RISC-V Foundation. He is an ACM Distinguished Scientist and an IEEE Fellow. Krste Received a PhD from UC Berkeley and a BA from the University of Cambridge. 

This webinar provided an introduction to RISC-V, covering areas such as the Register File, Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior knowledge of RISC-V is not necessary, but having a basic understanding of Computer Architecture would be beneficial.

This webinar is for embedded developers who are interested in learning more about the RISC-V architecture. Part 3 walks users through downloading and evaluating SiFive RISC-V Core IP, including E31 Evaluation RTL, and using Freedom Studio to program and debug code running on the E31 FPGA evaluation

Part III: Evaluating SiFive RISC-V Core IP 

The SiFive 7-Series is now available with more performance, new features for security and mission-critical applications, and lower power thanks to the new 20G1 6.0 update. 

20G1Update_final.mp4

The SiFive 7-Series is now available with more performance, new features for security and mission-critical applications, and lower power thanks to the new 20G1 6.0 update. SiFive experts Drew Barbier and Dany Nativel are joined by Jeff Hancock of Mentor Graphics to give you the details of the unique capabilities of SiFive 7-Series Core IP and why they are important for customers building secure, mission-critical capable solutions.

Faster, More Efficient, Mission-Critical-ready 7-Series Core IP

SiFive_Secure_Debug_Technical_Paper_v1p1.pdf

WorldGuard-Technical-Paper_v2.1.pdf

System-level SoC software isolation security solution

MPR 12222.pdf

SiFive Shield and SiFive WorldGuard Provide Open Secure Platform Architecture

Series 7 Comprises First Superscalar RISC-V CPUs

SiFive U8 Takes RISC-V Out of Order.pdf

U84 Is First in New Series of High-Performance RISC-V CPUs

Resources

Videos

Krste Asanovic on the Past, Present and Future of RISC-V and SiFive

ASPLOS Keynote: The Golden Age of Compiler Design in an Era of HW/SW Co-design

SiFive RISC-V Software Ecosystem, Featuring IAR Systems, Lauterbach, SEGGER, and more

SiFive Insight: Trace and Debug Solution

Webinars

LLM Optimization and Deployment on SiFive Intelligence

Rapid Embedded Prototyping with SiFive Software

SiFive 21G1 Release Webinar

Technical Papers

SiFive Shield Secure Debug

SiFive WorldGuard Solution

SiFive Secures RISC-V

SiFive Raises RISC-V Performance

SiFive U8 Takes RISC-V Out Of Order

Case Studies

SiFive Shepherds RISC-V ISA to Enterprise Applications, Broader Adoption

SiFive P650 Pumps Up Performance by 50%