SiFive Performance
P650/P670

The latest generation SiFive Performance™ P600-Series processors taped out earlier this year and are the highest performance commercially licensable RISC-V processors.

The P670 vector application processor features a thirteen-stage, four-issue, out-of-order pipeline and offers best-in-class performance, with >50% uplift over the SiFive Performance P550, while maintaining a significant performance-per-area advantage compared to the Arm® Cortex®-A78.

For applications that don't require vector compute, or for more area-constrained markets, the P650 offers similar performance levels in a smaller area footprint.

SiFive Performance Family

  • Processor family delivering superior compute density and performance for modern workloads in an energy-efficient area footprint.
  • Mobile, Consumer, Datacenter and Edge Infrastructure

SiFive Performance
P600 Series Key Features

  • Full support for the RVA22 RISC-V profile specification and Vector 1.0 and Vector Crypto for enabling 64-bit apps processors running feature rich OS stacks such as Linux and Android.
  • Breakthrough RISC-V performance
    - Coherent, multi-core, multi-cluster processor configurations, with up to 16 cores
    - Highest performance commercially licensable RISC-V processor
  • >12 SpecINT2k6/GHz (P670 Processor)
    - 2x 128-bit RISC-V Vector ALUs compliant with the ratified v1.0RISC-V Vector specification
    - RISC-V Vector Cryptography extension
  • P600-Series Architectural Features
    - 64-bit RISC-V core with extensive Virtual Memory Support
    - Four-issue, out-of-order pipeline tuned for scalable performance
    - Private L2 Caches and Streaming Prefetcher for improved memory performance
    - SECDED ECC with Error Reporting
  • Enabling next generation high performance applications
    - RISC-V Hypervisor Extension and System-Level Virtualization IP
    - Advanced interrupt controller with support for MSI style interrupts and virtualization
    - SiFive WorldGuard System Security
    - Cache stashing to L3 for tightly coupled accelerators

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